Add EmbeddedRiscvJtag noTap with tunnel support

SpinalHDL · Jul 17, 2024 · 49b3f9c · 49b3f9c
1 parent 11ff576
commit 49b3f9c
Showing 1 changed file with 11 additions and 1 deletion.
diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
@@ -15,7 +15,8 @@ import vexriscv._
 class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
                         var debugCd : ClockDomain = null,
                         var withTap : Boolean = true,
-                        var withTunneling : Boolean = false
+                        var withTunneling : Boolean = false,
+                        var jtagCd : ClockDomain = null
                         ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
 
 
@@ -69,6 +70,15 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
       dm.io.ctrl <> logic.io.bus
       logic.io.jtag <> jtag
     }
+    val dmiDirectInstr = if (!withTap && withTunneling) new Area {
+      val logic = DebugTransportModuleTunneled(
+        p.copy(addressWidth = 7),
+        debugCd = ClockDomain.current,
+        jtagCd = jtagCd
+      )
+      dm.io.ctrl <> logic.io.bus
+      logic.io.instruction <> jtagInstruction
+    }
 
     val privBus = pipeline.service(classOf[CsrPlugin]).debugBus.setAsDirectionLess()
     privBus <> dm.io.harts(0)