Fix CsrPlugin FPU access

SpinalHDL · Sep 20, 2024 · 7fac668 · 7fac668
1 parent 9dcf5c3
commit 7fac668
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -784,7 +784,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
         buffer.ready := injectionPort.fire
         val fpu = withDebugFpuAccess generate new Area {
           val access = service(classOf[FpuPlugin]).access
-          access.start := buffer.valid && buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE
+          access.start := buffer.valid && (buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE)
           access.regId := buffer.address
           access.write := buffer.op === DebugDmToHartOp.REG_WRITE
           access.writeData := dataCsrw.value.take(2).asBits