Fix #412 tightly coupled HAS_SIDE_EFFECT fix

SpinalHDL · Jun 17, 2024 · 8c191a2 · 8c191a2
1 parent 3ee790d
commit 8c191a2
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -473,7 +473,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       cache.io.cpu.memory.mmuRsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite)
 
       if(tightlyGen){
-        when(input(MEMORY_TIGHTLY).orR){
+        when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){
           cache.io.cpu.memory.isValid := False
           input(HAS_SIDE_EFFECT) := False
         }
@@ -585,7 +585,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       insert(MEMORY_LOAD_DATA) := rspShifted
 
       if(tightlyGen){
-        when(input(MEMORY_TIGHTLY).orR){
+        when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){
           cache.io.cpu.writeBack.isValid := False
           exceptionBus.valid := False
           redoBranch.valid := False