4bit_magnitude_comparator(dvsd_cmp) RTL2GDS flow

The purpose of this project is to produce a clean GDS (Graphic Design System) Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL (Register-Transfer Level) of an 4bit magnitude comparator, using SkyWater 130nm PDK (Process Design Kit)

Table of Contents

• Design
• Pin Configuration
• Pre-layout Simulation
• Openlane Workflow
• OpenLane
• OpenLane design stages
• Installation
  • Setting OpenLane
  • Install SKY130 PDK
  • Test
  • Opening OpenLane in Docker
• Running openlane
• Magic layout generate
• Post-layout simulation
• Key points to Remember
• Area of improvement
• References
• Acknowledgement
• Author

Design

Pin Configuration

Pre-layout Simulation

This is how you can simulate your design.

Pre-layout simulation waveform

Openlane Workflow

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. For more information check here

OpenLane design stages

1. Synthesis
   • yosys - Performs RTL synthesis
   • abc - Performs technology mapping
   • OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   • init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   • ioplacer - Places the macro input and output ports
   • pdn - Generates the power distribution network
   • tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   • RePLace - Performs global placement
   • Resizer - Performs optional optimizations on the design
   • OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   • TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   • FastRoute - Performs global routing to generate a guide file for the detailed router
   • CU-GR - Another option for performing global routing.
   • TritonRoute - Performs detailed routing
   • SPEF-Extractor - Performs SPEF extraction
6. GDSII Generation
   • Magic - Streams out the final GDSII layout file from the routed def
   • Klayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Checks
   • Magic - Performs DRC Checks & Antenna Checks
   • Klayout - Performs DRC Checks
   • Netgen - Performs LVS Checks
   • CVC - Performs Circuit Validity Checks

Installation

Preferred Prerequisites

• Preferred Ubuntu OS)
• Docker 19.03.12+
• GNU Make
• Python 3.6+ with PIP
• Click, Pyyaml: pip3 install pyyaml click

Setting OpenLane

git clone https://github.com/efabless/openlane.git openlane
cd openlane 
make openlane 
make pdk

Install SKY130 PDK

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>

Installed and add this configuration variable

export STD_CELL_LIBRARY=<Library name>

the library names is one of:

• sky130_fd_sc_hd
• sky130_fd_sc_hs
• sky130_fd_sc_ms
• sky130_fd_sc_ls
• sky130_fd_sc_hdll

you can install all SKY130

make full-pdk

Test

On successful completion of previous step, lets test it by

make test

which shall display the "successful" message.

Note: Go to next steps only after having the successful test.

Next steps

Opening OpenLane in Docker

If docker is installed, if you can see the docker version 19.* and above then docker is present and go to next step else install docker manually

docker --version

you can install docker file following this link

https://docs.docker.com/engine/install/

Running openlane

Once you are sure the docker is present, you have to make mount of the current files in openlane

make mount

Now lets test a design which is already present in openlane/designs type The following directory of design where the design is present is : 'vsdflow/work/tools/openlane_working_dir/openlane/designs/dvsd_cmp'

bash-4:$

./flow.tcl -design dvsd_cmp -tag vanshika_4bit_magnitude_comparator

which shall display the "successful" message after running all the respective tasks.

Magic layout generate

For magic layout generation in magic tool write this in terminal where you ran the above process

bash-4:$

magic dvsd_cmp.mag

Zoom-in view of IP Layout of dvsd_cmp design in Magic Tool.

Zoom-out view of IP Layout of dvsd_cmp design in Magic Tool.

Post-layout simulation

command for post-layout simulation

Post-layout simulation waveform

Key points to Remember

• Keep the top module name and design name always same, else errors would come in the design.

Area of improvement

• To perform spice simulation of the final GDS layout.

References

• GitLab/OpenLane workshop
• The OpenROAD Project/OpenLane
• Ahmed Ghazy and Mohamed Shalan, "OpenLane: The Open-Source Digital ASIC Implementation Flow", Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. Paper
• YOUTUBE/OpenLane Overview
• GitHUB/openlane_build_script
• GitLab/OpenLANE-Sky130-Physical-Design-Workshop

Acknowledgement

• Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd

Author

• Vanshika Tanwar, Bachelor of Technology in Electronics & Communication Engineering,Dronacharya Group of Institutions,Greater Noida, U.P.