Skip to content

This project produced a clean GDS - Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.

License

Notifications You must be signed in to change notification settings

VanshikaTanwar/dvsd_pe_sky130

 
 

Repository files navigation

license

8 bit Priority Encoder (dvsd_pe_sky130) RTL2GDS flow using SKY130 pdks

The purpose of this project is to produce a clean GDS (Graphic Design System) Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL (Register-Transfer Level) of an 8-bit Priority Encoder, using SkyWater 130 nm PDK (Process Design Kit)

Table of Contents

Design Overview

Slide2

IP specs provided

Slide4

For detailed IP specs, click here

Verilog behavioral design

Yosys synthesis

synthesis_dot

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. For more information check here

openlane flow 1

OpenLane design stages

  1. Synthesis
    • yosys - Performs RTL synthesis
    • abc - Performs technology mapping
    • OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
  2. Floorplan and PDN
    • init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
    • ioplacer - Places the macro input and output ports
    • pdn - Generates the power distribution network
    • tapcell - Inserts welltap and decap cells in the floorplan
  3. Placement
    • RePLace - Performs global placement
    • Resizer - Performs optional optimizations on the design
    • OpenDP - Perfroms detailed placement to legalize the globally placed components
  4. CTS
    • TritonCTS - Synthesizes the clock distribution network (the clock tree)
  5. Routing
    • FastRoute - Performs global routing to generate a guide file for the detailed router
    • CU-GR - Another option for performing global routing.
    • TritonRoute - Performs detailed routing
    • SPEF-Extractor - Performs SPEF extraction
  6. GDSII Generation
    • Magic - Streams out the final GDSII layout file from the routed def
    • Klayout - Streams out the final GDSII layout file from the routed def as a back-up
  7. Checks
    • Magic - Performs DRC Checks & Antenna Checks
    • Klayout - Performs DRC Checks
    • Netgen - Performs LVS Checks
    • CVC - Performs Circuit Validity Checks

Installation

Prerequisites

  • Preferred Ubuntu OS)
  • Docker 19.03.12+
  • GNU Make
  • Python 3.6+ with PIP
  • Click, Pyyaml: pip3 install pyyaml click
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
make openlane
make pdk
make test # This a ~5 minute test that verifies that the flow and the pdk were properly installed

For detailed installation process, check here

Running OpenLane

make mount

  • Note
    • Default PDK_ROOT is $(pwd)/pdks. If you have installed the PDK at a different location, run the following before make mount:
    • Default IMAGE_NAME is efabless/openlane:current. If you want to use a different version, run the following before make mount:

The following is roughly what happens under the hood when you run make mount + the required exports:

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
export IMAGE_NAME=<docker image name>
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME

You can use the following example to check the overall setup:

./flow.tcl -design spm

To run openlane in interactive mode

./flow.tcl -interactive

openlane_interactive

Pre-layout

Simulation

Terminal snap (To perform pre-layout simulation)

prelayterm

GTKWave output waveform

pre_layout_sim

Synthesis

synth_explore

Synthesis reports


- Printing statistics.

=== dvsd_pe ===

   Number of wires:                 53
   Number of wire bits:             64
   Number of public wires:           5
   Number of public wire bits:      14
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 55
     $_ANDNOT_                      10
     $_AND_                          1
     $_DLATCH_N_                     3
     $_NAND_                         3
     $_NOR_                          4
     $_ORNOT_                        9
     $_OR_                          25


- Printing statistics.

=== dvsd_pe ===

   Number of wires:                 35
   Number of wire bits:             44
   Number of public wires:           5
   Number of public wire bits:      14
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 35
     sky130_fd_sc_hd__a21oi_2        1
     sky130_fd_sc_hd__a2bb2o_2       1
     sky130_fd_sc_hd__a31o_2         1
     sky130_fd_sc_hd__buf_1          5
     sky130_fd_sc_hd__dlxtn_1        3
     sky130_fd_sc_hd__inv_2          8
     sky130_fd_sc_hd__o21ai_2        1
     sky130_fd_sc_hd__o22a_2         2
     sky130_fd_sc_hd__o22ai_2        1
     sky130_fd_sc_hd__o2bb2a_2       1
     sky130_fd_sc_hd__o41a_2         2
     sky130_fd_sc_hd__or2_2          1
     sky130_fd_sc_hd__or3_2          2
     sky130_fd_sc_hd__or4_2          4
     sky130_fd_sc_hd__or4b_2         2

   Chip area for module '\dvsd_pe': 276.515200

  • Yosys synthesis strategies

synhesisstrategies

exploration-2

Floorplanning


# User config
set ::env(DESIGN_NAME) dvsd_pe

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""

set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 0

set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 34.165 54.885"
set ::env(PL_TARGET_DENSITY) 0.75

set ::env(FP_HORIZONTAL_HALO) 6
set ::env(FP_VERTICAL_HALO) $::env(FP_HORIZONTAL_HALO)

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

floorplan_final

Placement

  • Placement Analysis
---------------------------------
total displacement        274.2 u
average displacement        3.5 u
max displacement           33.8 u
original HPWL             639.8 u
legalized HPWL            838.1 u
delta HPWL                   31 %

  • Routing resources analysis
          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical          420           396          5.71%
met1       Horizontal        560           380          32.14%
met2       Vertical          420           432          -2.86%
met3       Horizontal        280           234          16.43%
met4       Vertical          168           167          0.60%
met5       Horizontal         56            42          25.00%
---------------------------------------------------------------

  • Final congestion report

Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1                396            31            7.83%             0 /  0 /  0
met1               380            26            6.84%             0 /  0 /  0
met2               432             4            0.93%             0 /  0 /  0
met3               234             0            0.00%             0 /  0 /  0
met4               167             0            0.00%             0 /  0 /  0
met5                42             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total             1651            61            3.69%             0 /  0 /  0

placement_final

Routing

  • Routing resurces analysis

          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical          420           168          60.00%
met1       Horizontal        560           384          31.43%
met2       Vertical          420           432          -2.86%
met3       Horizontal        280           234          16.43%
met4       Vertical          168           167          0.60%
met5       Horizontal         56            42          25.00%
---------------------------------------------------------------

  • Final congestion report

Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1                168            31           18.45%             0 /  0 /  0
met1               384            43           11.20%             0 /  0 /  0
met2               432            36            8.33%             0 /  0 /  0
met3               234             0            0.00%             0 /  0 /  0
met4               167             0            0.00%             0 /  0 /  0
met5                42             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total             1427           110            7.71%             0 /  0 /  0

  • Complete detail routing

total wire length = 874 um
total wire length on LAYER li1 = 62 um
total wire length on LAYER met1 = 341 um
total wire length on LAYER met2 = 438 um
total wire length on LAYER met3 = 31 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 297
up-via summary (total 297):

----------------------
 FR_MASTERSLICE      0
            li1    153
           met1    138
           met2      6
           met3      0
           met4      0
----------------------
                   297

Final Summary


Run Directory: /openLANE_flow/designs/dvsd_pe/runs/run
----------------------------------------

Magic DRC Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/magic//31-magic.drc
Total Magic DRC violations is 0
----------------------------------------

LVS Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/results/lvs/dvsd_pe.lvs_parsed.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------

Antenna Summary:
Source: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/routing//33-antenna.rpt
Number of pins violated: 0
Number of nets violated: 0
[INFO]: check full report here: /openLANE_flow/designs/dvsd_pe/runs/run3/reports/final_summary_report.csv
[INFO]: Saving Runtime Environment
[SUCCESS]: Flow Completed Without Fatal Errors.

Layout vs Schematic

  • Subcircuit summary
Circuit 1: dvsd_pe                         |Circuit 2: dvsd_pe                         
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__fill_2 (1)                |sky130_fd_sc_hd__fill_2 (1)                
sky130_fd_sc_hd__nand2_1 (1)               |sky130_fd_sc_hd__nand2_1 (1)               
sky130_fd_sc_hd__decap_4 (1)               |sky130_fd_sc_hd__decap_4 (1)               
sky130_fd_sc_hd__o21ai_1 (1)               |sky130_fd_sc_hd__o21ai_1 (1)               
sky130_fd_sc_hd__clkbuf_2 (5)              |sky130_fd_sc_hd__clkbuf_2 (5)              
sky130_fd_sc_hd__fill_1 (1)                |sky130_fd_sc_hd__fill_1 (1)                
sky130_fd_sc_hd__a21oi_1 (2)               |sky130_fd_sc_hd__a21oi_1 (2)               
sky130_fd_sc_hd__decap_8 (1)               |sky130_fd_sc_hd__decap_8 (1)               
sky130_fd_sc_hd__or4_1 (1)                 |sky130_fd_sc_hd__or4_1 (1)                 
sky130_fd_sc_hd__buf_1 (8)                 |sky130_fd_sc_hd__buf_1 (8)                 
sky130_fd_sc_hd__decap_6 (1)               |sky130_fd_sc_hd__decap_6 (1)               
sky130_fd_sc_hd__a2111o_1 (1)              |sky130_fd_sc_hd__a2111o_1 (1)              
sky130_fd_sc_hd__decap_3 (1)               |sky130_fd_sc_hd__decap_3 (1)               
sky130_fd_sc_hd__inv_2 (6)                 |sky130_fd_sc_hd__inv_2 (6)                 
sky130_fd_sc_hd__dlxtn_1 (3)               |sky130_fd_sc_hd__dlxtn_1 (3)               
sky130_fd_sc_hd__or2_1 (2)                 |sky130_fd_sc_hd__or2_1 (2)                 
sky130_fd_sc_hd__o2bb2a_1 (1)              |sky130_fd_sc_hd__o2bb2a_1 (1)              
sky130_fd_sc_hd__clkbuf_1 (4)              |sky130_fd_sc_hd__clkbuf_1 (4)              
sky130_fd_sc_hd__dlymetal6s2s_1 (1)        |sky130_fd_sc_hd__dlymetal6s2s_1 (1)        
sky130_fd_sc_hd__tapvpwrvgnd_1 (1)         |sky130_fd_sc_hd__tapvpwrvgnd_1 (1)         
sky130_fd_sc_hd__o22ai_1 (2)               |sky130_fd_sc_hd__o22ai_1 (2)               
sky130_fd_sc_hd__or3_1 (3)                 |sky130_fd_sc_hd__or3_1 (3)                 
sky130_fd_sc_hd__o41a_1 (2)                |sky130_fd_sc_hd__o41a_1 (2)                
sky130_fd_sc_hd__or3b_1 (1)                |sky130_fd_sc_hd__or3b_1 (1)                
sky130_fd_sc_hd__a2bb2o_1 (1)              |sky130_fd_sc_hd__a2bb2o_1 (1)              
sky130_fd_sc_hd__o22a_1 (1)                |sky130_fd_sc_hd__o22a_1 (1)                
sky130_fd_sc_hd__or4b_1 (1)                |sky130_fd_sc_hd__or4b_1 (1)                
Number of devices: 54                      |Number of devices: 54                      
Number of nets: 58                         |Number of nets: 58                         
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.
  • Subcircuits pins

Circuit 1: dvsd_pe                         |Circuit 2: dvsd_pe                         
-------------------------------------------|-------------------------------------------
in[0]                                      |in[0]                                      
in[1]                                      |in[1]                                      
in[2]                                      |in[2]                                      
in[5]                                      |in[5]                                      
in[4]                                      |in[4]                                      
in[3]                                      |in[3]                                      
en                                         |en                                         
in[6]                                      |in[6]                                      
in[7]                                      |in[7]                                      
eno                                        |eno                                        
out[2]                                     |out[2]                                     
out[0]                                     |out[0]                                     
out[1]                                     |out[1]                                     
gs                                         |gs                                         
VGND                                       |VGND                                       
VPWR                                       |VPWR                                       
---------------------------------------------------------------------------------------

Final Layout

  • Layout after floorplanning and placement in Magic

placement

  • Final GDS layout

magic

  • Closeup view of the final layout design

layoutwoplace

  • lef layout

lef

  • tkcon window

tkon

Post-layout

Simulation

Terminal snap (To perform post-layout simulation)

postlayterm

GTKWave output waveform

postsynthwave

Steps to reproduce and explore the design

  • Clone the project using following command

git clone https://github.com/Khalique13/dvsd-8-bit-priority-encoder.git

  • To explore synthesis of the design
make mount
flow.tcl -design dvsd_pe -synth_explore
  • To reproduce Pre-layout simulation
cd pre_layout/
iverilog -o dvsd_pe dvsd_pe.v test_dvsd_pe.v
./dvsd_pe
gtkwave dvsd_pe.vcd
  • To explore floorplan
cd floorplan/
magic lef read merged.lef def read dvsd_pe.floorplan.def &
  • To explore placement
cd placement/ 
magic lef read merged.lef def read dvsd_pe.placement.def &
  • To explore final layout
cd final_layout/
magic dvsd_pe.mag
  • To reproduce Post-layout simulation
cd post_layout/
iverilog -o gls -DFUNCTIONAL -DUNIT_DELAY=#1 gls.v primitives.v sky130_fd_sc_hd.v
./gls
gtkwave gls.vcd
  • Complete details, logs and results can be found under this folder.
dvsd_pe
├── config.tcl
├── runs
│   ├── run
│   │   ├── config.tcl
│   │   ├── logs
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── reports
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   └── tmp
│   │       ├── cts
│   │       ├── cvc
│   │       ├── floorplan
│   │       ├── klayout
│   │       ├── magic
│   │       ├── placement
│   │       ├── routing
│   │       └── synthesis

Key points to Remember

  • Keep the top module name and design name always, else errors would come in the design.
  • This project is a Combinaional block hence there is no clock, static time analysis is being skiped.

Area of improvement

  • Improvement in the design and integration of Power pins.
  • To perform spice simulation of the final GDS layout.

References

Acknowledgement

Author

About

This project produced a clean GDS - Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages

  • Verilog 97.6%
  • Tcl 2.0%
  • Other 0.4%