[RWRoute] Versal optimizations #1093

WenhaoLin-AMD · 2024-11-04T07:00:01Z

This PR:

Applies [RWRoute] Divide nodes into LOCAL and NON_LOCAL #1095 to Versal nodes based on their intent codes -- ensuring that NON_LOCAL -> LOCAL node transition only happens in the vicinity of the sink tile
- With special handling for NODE_(CLE|INTF)_[BC]NODE nodes to prevent them from being used to travel between INT tiles, but still used to "bounce" (back) into the original (sink) tile
Further applies [RWRoute] Further divide LOCAL nodes into EAST/WEST for UltraScale(+) #1098 to Versal nodes based on their wire or tile name to ensure that only the relevant east/west side of the INT tile is explored
- Note that NODE_CLE_[BC]NODE nodes can reach NODE_INODEs on the opposite side of the former's wire name
Add a RouteNodeType.LOCAL_RESERVED as part of a Versal-only heuristic to reserve [BC]NODEs uphill of a NODE_(CLE|INTF)_CTRL sink, since [BC]NODEs (especially CNODEs) are the only way to reach CTRL sinks, while also providing extra connectivity to NODE_INODEs in the INT tile.
- e.g. On 1c2b471, for finn_radioml using LOCAL_RESERVED requires 119M pops over 10 iterations to route, but without needed 176M pops over 17 iterations.
- The downside to this heuristic is that all CNODEs are reserved for even one CTRL sink, meaning that just one sink will prevent any other nets from using those CNODEs

Results:

			Before (a3af7dc)		After (1c2b471)	
			Nodes popped	Runtime (s)	Nodes popped	Runtime (s)
boom_med_pb		  308,212,121	 201		 92,043,436	 79
boom_soc		3,320,844,555	2184		831,951,144	698
corescore_500		  381,326,217	 249		141,432,563	133
corescore_500_pb	  393,285,727	 260		147,020,615	137
finn_radioml		  401,124,667	 253		118,592,148	101
koios_dla_like_large	1,329,175,620	 923		270,148,933	263
logicnets_jscl		   85,632,115	  58		 42,305,715	 33
vtr_lu64peeng		  429,006,483	 295		194,564,833	175
vtr_mcml		  185,015,595	 127		 79,474,273	 71

Overall, 2.7x improvement in wall clock RWRoute runtime, 3.6x the number of nodes popped.

Signed-off-by: Wenhao Lin <wenhao.lin@amd.com>

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Conflicts: src/com/xilinx/rapidwright/rwroute/Connection.java src/com/xilinx/rapidwright/rwroute/RWRoute.java src/com/xilinx/rapidwright/rwroute/RouteNode.java src/com/xilinx/rapidwright/rwroute/RouteNodeGraph.java src/com/xilinx/rapidwright/rwroute/RouteNodeInfo.java test/src/com/xilinx/rapidwright/device/TestNode.java

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Conflicts: src/com/xilinx/rapidwright/rwroute/RouteNode.java

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

src/com/xilinx/rapidwright/rwroute/RouteNodeGraph.java

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

WenhaoLin-AMD and others added 15 commits November 3, 2024 23:31

Add optimization of signal routing

f89c96e

Signed-off-by: Wenhao Lin <wenhao.lin@amd.com>

Merge new method into RoutingGraph.isAccessible()

57f39df

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Fix typo

74df324

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add TestNode.testNodeReachabilityVersal() to check assumptions

3bf9cb9

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add NODE_CLE_OUTPUT too

bf4d076

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Expand TestNode.testNodeReachabilityUltraScale()

1f8a9d3

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

More

bba91e1

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add and use RouteNodeType.LOCAL

4356b03

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Merge RouteNodeType.PINBOUNCE into LOCAL; rename WIRE, PINFEED_{I,O}

7e7015a

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

LUT routethru fixes

b9ff45f

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add testNodeReachabilityVersal()

aabab3c

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Support UltraScale

9929603

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Merge branch 'us_node_reach' into signal_router_optimize_eh

e47cd18

Extend RouteNodeType.LOCAL to Versal

9aba0ac

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Exclude Versal's NODE_IMUX/NODE_{CLE,INTF}_CTRL if not in RRG

c197f08

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

eddieh-xlnx mentioned this pull request Nov 5, 2024

[RWRoute] Divide nodes into LOCAL and NON_LOCAL #1095

Merged

eddieh-xlnx changed the title ~~Add optimization of signal routing~~ [RWRoute] Versal optimizations Nov 6, 2024

eddieh-xlnx added 12 commits November 6, 2024 23:22

More explanatory approach; no difference

7274b33

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Improvement?

14955fe

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Cleanup

56afd4b

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Update comments

cac787e

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add NODE_INTF_{CNODE,BNODE}

ef4227c

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

[TestNode] Expand testNodeReachabilityUltraScale

cd631ac

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Expand testNodeReachabilityVersal too

038aa80

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

UltraScale+: Sub-divide LOCALs into _EAST/_WEST and stick to sink's side

77fa308

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Re-add EXCLUSIVE_SINK (non-sided) for CTRL sinks

6229dbe

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Support UltraScale

74fdf59

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Print

a1dca37

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Expand testNodeReachabilityVersal

977b068

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

eddieh-xlnx added 16 commits November 12, 2024 16:24

Apply Xilinx#1098 to Versal too

c1e8274

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Assign CNODEs to be LOCAL_{EAST,WEST} (opposite to name)

50287fe

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Merge branch 'master' into signal_router_optimize

b048ef3

Fix merge

f4df052

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Resolve FIXMEs

003a051

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Restore comment

c057226

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Fix continue

353775c

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

On Versal, make all NODE_PINFEEDs RouteNodeType.LOCAL

a9f5161

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Handle NODE_INTF_CNODE too

76bc5cc

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add comment

7b190bf

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Simplify if

e877503

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Introduce LOCAL_RESERVED

ce90eb7

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Allow INODE and PINBOUNCE either side of CTRL sink to be used

1c2b471

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Update comment

5414206

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Clearer names

57ed051

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Fix

8c0acba

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

eddieh-xlnx requested a review from clavin-xlnx November 13, 2024 23:33

eddieh-xlnx added 4 commits November 13, 2024 15:57

Tidy up

d1e843a

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Merge branch 'master' into signal_router_optimize

fb08d82

Conflicts: src/com/xilinx/rapidwright/rwroute/RouteNode.java

Use RouteNodeInfo.getType() with ignoreLaguna param

fc4499a

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Rename param to forceSink

9768314

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

clavin-xlnx reviewed Nov 14, 2024

View reviewed changes

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Address review comments

7e5ff64

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

eddieh-xlnx requested a review from clavin-xlnx November 14, 2024 17:57

Fix polarity of assert

ddbc814

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

clavin-xlnx approved these changes Nov 14, 2024

View reviewed changes

Tidy

025004b

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

eddieh-xlnx merged commit 07c7ceb into Xilinx:master Nov 14, 2024
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This was referenced Nov 21, 2024

Various preprocessing fixes for Versal routing #1112

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Various preprocessing fixes for Versal routing #1115

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[RWRoute] Versal optimizations #1093

[RWRoute] Versal optimizations #1093

WenhaoLin-AMD commented Nov 4, 2024 •

edited by eddieh-xlnx

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[RWRoute] Versal optimizations #1093

[RWRoute] Versal optimizations #1093

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WenhaoLin-AMD commented Nov 4, 2024 •

edited by eddieh-xlnx

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