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feat(CMSIS): Update MAX32657 CMSIS with TrustZone support #1008

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merged 8 commits into from
May 6, 2024

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sihyung-maxim
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@sihyung-maxim sihyung-maxim commented May 3, 2024

Description

Some updates to the CMSIS for Verification.

  • Added undecorated MXC_BASE_* definitions
  • Removed GET_S_ and GET_NS definitions from max32657.h
  • Define both DMA instances
  • Added partition_max32657.h (from CMSIS) to handle SAU memory region partitioning for secure and non-secure code.
  • Updated linker, startup, and system files (SystemInit, SAU, Stack Sealing, Interrupt Tables)

Both DMA0 and DMA1 need to be defined, so we can't use the single MXC_DMA instance anymore.

  1. DMA0 has a secure and non-secure mapping - accessible for secure and non-secure builds. However, DMA0 can not access secure memory or secure peripherals.
  2. DMA1 only has a secure mapping - accessible for secure builds. But DMA1 can access both secure or non-secure memory and peripherals.

I'll have a separate PR for the remaining SYS register updates that I need to make.

Edit: Removing multiple linkers comment, just saw your changes @Jake-Carter. But I don't think we need multiple vector table definitions and startup_max32657.S startup code.

We can have one vector table defined that includes all secure and non-secure handlers, and we can dynamically switch between secure and non-secure vector tables during startup process using the SCB->VTOR vector table offset register. The SCB->VTOR register is banked into two parts, and the appropriate offset for secure and non-secure is used depending on the security context. We can also explicitly label the secure-only interrupts with the _S names, and include a build warning/error if the non-secure application references a secure handler.

The secure vector table is set up in SystemInit() called from Reset_Handler on startup. We'd have to figure out a mechanism for non-secure builds (non-secure reset handler) to set up the non-secure vector table (using SCB->VTOR again). This is at least my current understanding of how we might go about this for our bare metal MSDK.

There's a lot to think about - but given our schedule and priorities, we can focus on handling the secure mode for now so verification can begin. These changes are geared towards finishing the Secure build system changes that you've made, and to prep the non-secure builds for down the road.

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@sihyung-maxim sihyung-maxim added the WIP work in progress label May 3, 2024
#define MXC_DMA_INSTANCES (1)
// ^ Note: We have 2 DMA instances in hardware, but they are secure vs non-secure
// instances. Therefore we treat the part as if there is only 1.
#define MXC_DMA_INSTANCES (2)
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If you try to build with this you'll see an issue at the bottom-level DMA driver file with the handler definitions. Also RevA depends on MXC_DMA

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Yes, that is why I added a WIP for this PR before committing to this.

// DMA0 can only access the non-secure mappings of the peripherals,
// but DMA0 can be accessed in both Non-secure and Secure code.
// DMA1 can access both secure and non-secure addresses of the peripherals,
// but DMA1 can Only be accessed in Secure code.
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DMA0 can be accessed from secure mode but my understanding is that the controller cannot access secure memory/peripherals. I think we should still preserve the ability to access it at the register-level, but for this first pass at the drivers I think we should revert back to the previous setup

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Yes, you are correct - as mentioned in the PR description above:

Both DMA0 and DMA1 need to be defined, so we can't use the single MXC_DMA instance anymore.

  1. DMA0 has a secure and non-secure mapping - accessible for secure and non-secure builds. However, DMA0 can not access secure memory or secure peripherals.
  2. DMA1 only has a secure mapping - accessible for secure builds. But DMA1 can access both secure or non-secure memory and peripherals.

The diction for all the security can get confusing. If we do a secure build, there needs to be an option to access both DMA0 and DMA1.

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What if we define MXC_DMA as DMA0/DMA1 based on the security level, set MXC_DMA_INSTANCES to 1, but still expose both base definitions of MXC_DMA0/MXC_DMA1?

#define MXC_DMA_CH_GET_IRQ(i) \
#define MXC_BASE_DMA0 MXC_BASE_DMA0_NS
#define MXC_DMA0 MXC_DMA0_NS
// TODO(DMA1): Not entirely show how to handle access to MXC_DMA1 in non-secure mode.
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The previous setup solves this problem as well

*(.ARM.extab* .gnu.linkonce.armextab.*)
_sg_veneers = .;
KEEP(*(.gnu.sgstubs*))
_esg_veneers = .;
} > FLASH_S
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See 4e9156e

I updated the linkerfile to support secure/non-secure from the same file. I think we should be able to wrap this section in the same way so that it only gets generated for the secure builds.

@github-actions github-actions bot added MAX32655 Related to the MAX32655 (ME17) MAX32670 Related to the MAX32670 (ME15) MAX32672 Related to the MAX32672 (ME21) MAX32675 Related to the MAX32675 (ME16) MAX32680 Related to the MAX32680 (ME20) MAX78000 Related to the MAX78000 (AI85) MAX78002 Related to the MAX78002 (AI87) MAX32662 Related to the MAX32662 (ME12) labels May 6, 2024
@@ -500,7 +500,11 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len
return retval;
}

#if (TARGET_NUM == 32657)
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:(

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Yep, agreed. I don't like this either lol. We can change this in another separate PR.

@Jake-Carter Jake-Carter merged commit 6397c85 into feat/ME30-PeriphDrivers May 6, 2024
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@Jake-Carter Jake-Carter deleted the feat/ME30-TZ branch May 6, 2024 22:55
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MAX32655 Related to the MAX32655 (ME17) MAX32662 Related to the MAX32662 (ME12) MAX32670 Related to the MAX32670 (ME15) MAX32672 Related to the MAX32672 (ME21) MAX32675 Related to the MAX32675 (ME16) MAX32680 Related to the MAX32680 (ME20) MAX78000 Related to the MAX78000 (AI85) MAX78002 Related to the MAX78002 (AI87) WIP work in progress
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