feat(CMSIS): Update MAX32657 CMSIS with TrustZone support

Libraries/CMSIS/Device/Maxim/GCC/gcc.mk

@@ -278,6 +278,8 @@ ifeq "$(MSECURITY_MODE)" "SECURE"
 # https://developer.arm.com/documentation/ecm0359818/latest
 PROJ_CFLAGS += -mcmse
 
+PROJ_AFLAGS += -DIS_SECURE_ENVRIONMENT
+
 # Tell the linker we are building a secure project.  This defines the "SECURE_LINK" symbol which the
 # linker uses to set the secure FLASH/SRAM memory address ranges.
 PROJ_LDFLAGS += -Xlinker --defsym=SECURE_LINK=1

Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h

@@ -474,8 +474,6 @@ typedef enum {
 #define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL)
 #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S)
 
-#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S
-
 #if IS_SECURE_ENVIRONMENT
 #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S
 #define MXC_GPIO0 MXC_GPIO0_S
@@ -654,11 +652,15 @@ We may want to handle GET_IRQ better...
 #define MXC_BASE_DMA1 MXC_BASE_DMA1_S
 #define MXC_DMA1 MXC_DMA1_S
 
-#define MXC_DMA1_CH_GET_IRQ(i)                \
-    ((IRQn_Type)(((i) == 0) ? DMA1_CH0_IRQn : \
-                 ((i) == 1) ? DMA1_CH1_IRQn : \
-                 ((i) == 2) ? DMA1_CH2_IRQn : \
-                 ((i) == 3) ? DMA1_CH3_IRQn : \
+#define MXC_DMA_CH_GET_IRQ(p, i)                \
+    ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \
+                 ((p) == MXC_DMA1 && (i) == 0) ? DMA1_CH0_IRQn : \
+                 ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \
+                 ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \
+                 ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \
                               0))
 
 #else
@@ -672,18 +674,16 @@ We may want to handle GET_IRQ better...
 #define MXC_DMA1 0
 
 /* DMA1 IRQs not usable in Non-Secure state. */
-#define MXC_DMA1_CH_GET_IRQ(i) ((IRQn_Type)(0))
+#define MXC_DMA_CH_GET_IRQ(p, i)                \
+    ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \
+                 ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \
+                              0))
 #endif // IS_SECURE_ENVIRONMENT
 
 #define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1)
 
-#define MXC_DMA0_CH_GET_IRQ(i)                \
-    ((IRQn_Type)(((i) == 0) ? DMA0_CH0_IRQn : \
-                 ((i) == 1) ? DMA0_CH1_IRQn : \
-                 ((i) == 2) ? DMA0_CH2_IRQn : \
-                 ((i) == 3) ? DMA0_CH3_IRQn : \
-                              0))
-
 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1)
 
 /******************************************************************************/

Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h

@@ -30,6 +30,8 @@
 
 #include "max32657.h"
 
+#if IS_SECURE_ENVIRONMENT
+
 /*
 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
 */
@@ -1278,4 +1280,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
 
 }
 
+#endif // IS_SECURE_EVIRONMENT
+
 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_

Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld

@@ -70,14 +70,12 @@ SECTIONS {
      * Secure Gatway (SG) veneers.
      *  All SG veneers are placed in the special output section .gnu.sgstubs.
      */
-#if SECURE_LINK
     .gnu.sgstubs :
     {
         _sg_veneers = .;
-        KEEP(*(.gnu.sgstubs*))
+        *(.gnu.sgstubs*)
         _esg_veneers = .;
     } > FLASH
-#endif
 
     .ARM.extab :
     {
@@ -161,15 +159,13 @@ SECTIONS {
      *  Stack Seal section is required for secure builds. Stack sealing protects
      *  secure stack from illegal access by non-secure code.
      */
-#if SECURE_LINK
     .stackseal (COPY):
     {
         . = ALIGN(8);
         __StackSeal = .;
         . = . + 8;
         . = ALIGN(8);
     } > SRAM
-#endif
 
     /**
      *   Set stack top to end of RAM, and stack limit move down by
@@ -185,10 +181,8 @@ SECTIONS {
      */
     .stack_dummy (COPY):
     {
-        *(.stack*)
-#if SECURE_LINK
+        KEEP(*(.stack*))
         *(.stackseal*)
-#endif
     } > SRAM
 
     .heap (COPY):

Libraries/PeriphDrivers/Include/MAX32657/aes.h

@@ -27,6 +27,7 @@
 /***** Includes *****/
 #include "aes_regs.h"
 #include "aeskeys_regs.h"
+#include "dma_regs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -89,9 +90,10 @@ typedef struct _mxc_aes_cipher_req_t {
 /**
  * @brief   Enable portions of the AES
  *
+ * @param   dma   DMA instance used for AES
  * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
  */
-int MXC_AES_Init(void);
+int MXC_AES_Init(mxc_dma_regs_t *dma);
 
 /**
  * @brief   Enable AES Interrupts
@@ -213,18 +215,20 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req);
  * 
  * @param   src_addr  source address
  * @param   len       number of words of data
+ * @param   dma       DMA instance to configue for AES
  * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
  */
-int MXC_AES_TXDMAConfig(void *src_addr, int len);
+int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma);
 
 /**
  * @brief   Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO.
  * 
  * @param   dest_addr destination address
  * @param   len       number of words of data
+ * @param   dma       DMA instance to configure for AES
  * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
  */
-int MXC_AES_RXDMAConfig(void *dest_addr, int len);
+int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma);
 
 /**
  * @brief   Perform encryption or decryption using DMA 

Libraries/PeriphDrivers/Include/MAX32657/crc.h

@@ -26,6 +26,7 @@
 
 /***** Includes *****/
 #include "crc_regs.h"
+#include "dma_regs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -63,10 +64,10 @@ typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t;
 /**
  * @brief   Enable portions of the CRC
  *
- *
+ * @param   dma   DMA Instance used for CRC calculation
  * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
  */
-int MXC_CRC_Init(void);
+int MXC_CRC_Init(mxc_dma_regs_t *dma);
 
 /**
  * @brief   Disable and reset portions of the CRC

Libraries/PeriphDrivers/Include/MAX32657/dma.h

@@ -193,25 +193,30 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest);
  *             if you wish to manage clock and gpio related things in upper level instead of here.
  *             Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 
  *             By this flag this function will remove clock and gpio related codes from file.
+ * @param      dma  Pointer to selected DMA instance's registers.
+ * 
  * @return     #E_NO_ERROR if successful
  */
-int MXC_DMA_Init(void);
+int MXC_DMA_Init(mxc_dma_regs_t *dma);
 
 /**
  * @brief      De-Initialize DMA resources.
+ * 
+ * @param      dma  Pointer to selected DMA instance's registers.
  */
-void MXC_DMA_DeInit(void);
+void MXC_DMA_DeInit(mxc_dma_regs_t *dma);
 
 /**
  * @brief      Request DMA channel
  * @details    Returns a handle to the first free DMA channel, which can be used via API calls
  *             or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function.
+ * @param      dma  Pointer to selected DMA instance's registers.
  * @return     Non-negative channel handle (inclusive of zero).
  * @return     #E_NONE_AVAIL    All channels in use.
  * @return     #E_BAD_STATE     DMA is not initialized, call MXC_DMA_Init() first.
  * @return     #E_BUSY          DMA is currently busy (locked), try again later.
  */
-int MXC_DMA_AcquireChannel(void);
+int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma);
 
 /**
  * @brief      Release DMA channel
@@ -360,19 +365,21 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags);
  * @brief      Enable channel interrupt
  * @note       Each channel has two interrupts (complete, and count to zero)
                which must also be enabled with MXC_DMA_SetChannelInterruptEn()
+ * @param      dma  DMA instance used for the DMA channel registers.
  * @param      ch   DMA channel to enable interrupts for.
  * @return     #E_BAD_PARAM if an unused or invalid channel handle, 
  *             #E_NO_ERROR otherwise, \ref MXC_Error_Codes
  */
-int MXC_DMA_EnableInt(int ch);
+int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch);
 
 /**
  * @brief      Disable channel interrupt
+ * @param      dma  DMA instance used for the DMA channel registers.
  * @param      ch   DMA channel to disable interrupts for.
  * @return     #E_BAD_PARAM if an unused or invalid channel handle, 
  *             #E_NO_ERROR otherwise, \ref MXC_Error_Codes 
  */
-int MXC_DMA_DisableInt(int ch);
+int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch);
 
 /**
  * @brief      Start transfer
@@ -402,10 +409,11 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch);
 
 /**
  * @brief      Interrupt handler function
+ * @param 	   dma 	Pointer to DMA registers.
  * @details    Call this function as the ISR for each DMA channel under driver control.
  *             Interrupt flags for channel ch will be automatically cleared before return.
  */
-void MXC_DMA_Handler(void);
+void MXC_DMA_Handler(mxc_dma_regs_t *dma);
 
 /*************************/
 /* High Level Functions  */
@@ -416,27 +424,30 @@ void MXC_DMA_Handler(void);
  * @note       The user must have the DMA interrupt enabled and call
  *             MXC_DMA_Handler() from the ISR.
  *
+ * @param 	   dma 	Pointer to DMA registers.
  * @param      dest     pointer to destination memory
  * @param      src      pointer to source memory
  * @param      len      number of bytes to copy
  * @param      callback function to call when transfer is complete
  *
  * @return     see \ref MXC_Error_Codes
  */
-int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback);
+int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len,
+                   mxc_dma_complete_cb_t callback);
 
 /**
  * @brief      Performs a memcpy, using DMA, optionally asynchronous
  * @note       The user must have the DMA interrupt enabled and call
  *             MXC_DMA_Handler() from the ISR.
  *
+ * @param 	   dma 	Pointer to DMA registers.
  * @param      config   The channel config struct
  * @param      firstSrcDst  The source, destination, and count for the first transfer
  * @param      callback function is called when transfer is complete
  *
  * @return     see \ref MXC_Error_Codes
  */
-int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
+int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
                        mxc_dma_trans_chain_t callback);
 /**
  * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver

Libraries/PeriphDrivers/Include/MAX32657/spi.h

@@ -32,6 +32,7 @@
 #include "gpio.h"
 #include "mxc_pins.h"
 #include "mxc_lock.h"
+#include "dma_regs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -595,11 +596,12 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req);
  * possible. The channel will be reset and returned to the system at the end of
  * the transaction.
  *
- * @param   req             Pointer to details of the transaction
+ * @param   req     Pointer to details of the transaction
+ * @param   dma     DMA instance to use for SPI DMA
  *
  * @return  See \ref MXC_Error_Codes for the list of error return codes.
  */
-int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req);
+int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma);
 
 /**
  * @brief   Performs a blocking SPI transaction.
@@ -642,10 +644,11 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req);
  * the transaction.
  *
  * @param   req             Pointer to details of the transaction
+ * @param   dma             DMA instance to use for SPI DMA
  *
  * @return  See \ref MXC_Error_Codes for the list of error return codes.
  */
-int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req);
+int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma);
 
 /**
  * @brief   Sets the TX data to transmit as a 'dummy' byte

Libraries/PeriphDrivers/Include/MAX32657/uart.h

@@ -31,6 +31,7 @@
 #include <stdbool.h>
 #include "uart_regs.h"
 #include "mxc_sys.h"
+#include "dma_regs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -377,14 +378,15 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un
 /**
  * @brief   Unloads bytes from the receive FIFO user DMA for longer reads.
  *
- * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   uart        Pointer to UART registers (selects the UART block used).
+ * @param   dma         Pointer to DMA registers (selects the DMA block used for UART DMA).
  * @param   bytes       The buffer to read the data into.
  * @param   len         The number of bytes to read.
  * @param   callback    The function to call when the read is complete
  *
  * @return  See \ref MXC_Error_Codes for a list of return values
  */
-int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
+int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len,
                            mxc_uart_dma_complete_cb_t callback);
 
 /**
@@ -410,14 +412,15 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, u
 /**
  * @brief   Loads bytes into the transmit FIFO using DMA for longer writes
  *
- * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   uart        Pointer to UART registers (selects the UART block used).
+ * @param   dma         Pointer to DMA registers (selects the DMA block used for UART DMA).
  * @param   bytes       The buffer containing the bytes to write
  * @param   len         The number of bytes to write.
  * @param   callback    The function to call when the write is complete
  *
  * @return  See \ref MXC_Error_Codes for a list of return values
  */
-int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
+int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len,
                             mxc_uart_dma_complete_cb_t callback);
 
 /**
@@ -602,10 +605,11 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req);
  *          returned to the system at the end of the transaction.
  *
  * @param   req             Pointer to details of the transaction
+ * @param   dma             Pointer to DMA registers used for UART DMA
  *
  * @return  See \ref MXC_Error_Codes for the list of error return codes.
  */
-int MXC_UART_TransactionDMA(mxc_uart_req_t *req);
+int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma);
 
 /**
  * @brief   The processing function for DMA transactions.

Libraries/PeriphDrivers/Source/AES/aes_ai87.c

@@ -138,12 +138,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req)
 
 int MXC_AES_TXDMAConfig(void *src_addr, int len)
 {
-    return MXC_AES_RevB_TXDMAConfig(src_addr, len);
+    return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA);
 }
 
 int MXC_AES_RXDMAConfig(void *dest_addr, int len)
 {
-    return MXC_AES_RevB_RXDMAConfig(dest_addr, len);
+    return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA);
 }
 
 int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc)