Merge pull request riscv#549 from leesum1/trigger-fix

debug: Fix nonexistent trigger registers trap handle in entry.S
billmcspadden-riscv · May 9, 2024 · 29e6bc8 · 29e6bc8
2 parents 7dfa49b + 7f454c3
commit 29e6bc8
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/debug/programs/entry.S b/debug/programs/entry.S
@@ -84,8 +84,9 @@ handle_reset:
   beq   t0, t1, 1b
 .p2align 2
 2:
-  # Restore mtvec
+  # Restore mtvec and mstatus
   csrw mtvec, t2
+  csrwi mstatus, 0
 
 #ifdef MULTICORE
   csrr  t0, CSR_MHARTID