Format code style

chipsalliance · Dec 22, 2024 · 4ceb064 · 4ceb064
1 parent e68c1ea
commit 4ceb064
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/chisel3/util/MuxImpl.scala b/src/main/scala/chisel3/util/MuxImpl.scala
@@ -47,7 +47,7 @@ object Mux1H {
   * Returns the output of the Mux tree.
   */
 object PriorityMux {
-  def apply[T <: Data](in:  Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
+  def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
   def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = {
     require(sel.size == in.size, "PriorityMux: Number of select signals and inputs must match")
     apply(sel.zip(in))