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Add input seq length check to Mux1H and PriorityMux #4572

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@Emin017 Emin017 commented Dec 22, 2024

Added a new require to check that the input sequences have the same length in both Mux1H and PriorityMux implementations.

Fix #2181 and #4444 .

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Added a new require to check that the input sequences have the same
length in both Mux1H and PriorityMux implementations.
@Emin017 Emin017 force-pushed the mux-input-seqs-require branch from 6050d78 to e68c1ea Compare December 22, 2024 16:07
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Thanks for the tests! Can you enhance the error message to include the mismatching sizes?

src/main/scala/chisel3/util/MuxImpl.scala Outdated Show resolved Hide resolved
@Emin017 Emin017 force-pushed the mux-input-seqs-require branch from dca58e1 to 18d41e4 Compare December 23, 2024 00:54
@Emin017 Emin017 requested a review from mwachs5 December 23, 2024 01:28
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Mux1H should verify that sel and in are the same length
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