Chisel v6.1.0

Features

• Support checking isVisible with reflect.DataMirror (by @poemonsense in #3753)
• Provide ImplicitClock and ImplicitReset (backport #3714) (by @mergify[bot] in #3769)
  These traits implement the functionality formerly only implemented in Module such that they can now be used by RawModules. They also define new protected virtual methods implicitClock and implicitReset that can be overridden within Module to change what values are used as the implicit clock and implicit reset respectively.
• Support isLit for Property types. (backport #3782) (by @mergify[bot] in #3789)
  Since we override litOption to always be None, we need to override isLit to check the Binding.
• Support isProperty query in DataMirror. (backport #3783) (by @mergify[bot] in #3790)
  This adds an API to DataMirror to query if a Data is a Property.
• Support Property in BoringUtils. (backport #3784) (by @mergify[bot] in #3791)
  This adds support for BoringUtils.bore to bore and connect Property ports.
• Add a new DynamicObject.apply method to create Class instances. (backport #3792) (by @mergify[bot] in #3797)
  This is in addition to the existing support in Definition.apply. Sometimes it is not possible to use Definition.apply, for example, if you plan to bore ports through the Class being constructed. The new DynamicObject.apply method supports this, and creates a DynamicObject from the newly elaborated Class.
• Make SRAMInterface parameters publicly available (backport #3826) (by @mergify[bot] in #3828)
  memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.
• Add Property expressions, starting with addition. (backport #3810) (by @mergify[bot] in #3843)
  This allows Properties to be used to build up expressions in terms of input Properties and literals.
• Add Property expression for integer multiplication. (backport #3844) (by @mergify[bot] in #3845)
  This adds an API for integer Property multiplication.
• Add Property expression for integer shift right. (backport #3846) (by @mergify[bot] in #3850)
  This adds an API for integer Property shift right.
• Add DataProduct for Iterables and primitive types (backport #3856) (by @mergify[bot] in #3860)

Fixes

• Support === on empty Aggregates (by @jackkoenig in #3747)
• Fix Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in #3780)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #3804) (by @mergify[bot] in #3808)
• Fix visibility for views (backport #3818) (by @mergify[bot] in #3821)
  DataMirror.isVisible and other things checking visibility now work properly for views.
• [svsim] Better error message when verilator not on PATH (backport #3829) (by @mergify[bot] in #3833)
• Remove extra bit from SRAMInterface address width (backport #3830) (by @mergify[bot] in #3840)
• [svsim] Make EphemeralSimulator multi-processing friendly (backport #3847) (by @mergify[bot] in #3849)
  • Grab a unique temporary directory for every invocation using Java API
  • Allow multiple EphemeralSimulators to run in the same JVM (no longer necessary to single-thread)
  • Use pure Scala code to recursively delete directory at end rather than platform specific rm -rf

Documentation

• [docs] Minor updates to README and SETUP for Chisel 6 (by @jackkoenig in #3745)
• Update CONTRIBUTING.md (backport #3785) (by @mergify[bot] in #3788)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.

Dependency Updates

• de-bump to sbt 1.9.7 (backport #3852) (by @mergify[bot] in #3854)
  De-bumping to sbt 1.9.7 to avoid glibc issues for users, manifesting as:

  java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
  

• Add Scala 2.13.13 to cross-build (backport #3851) (by @mergify[bot] in #3864)

Build and Internal Changes

• [main] Enable MiMa for v6.0.0 (by @chiselbot in #3743)
• Enhance release notes automation (by @jackkoenig in #3751)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template
• Update Scala CLI Template (backport #3757) (by @mergify[bot] in #3861)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows

Full Changelog: v6.0.0...v6.1.0

Chisel v6.0.0

Features

• Add ConstType and Const(...) API (by @debs-sifive in #3046)
  Adds Const() API to create ConstTypes, which denotes Data that holds a constant value.
• Implement read-write memory accessors for SyncReadMem (by @jared-barocsi in #3190)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• [Feature] Add Interface, ConformsTo for Separate Compilation (by @seldridge in #3199)
• Handle BoringUtils in Chisel, rather than in FIRRTL compiler (by @azidar in #3187)
  Added a new BoringUtils.bore that is performed during Chisel elaboration, not via Annotations+CIRCT. Punched ports are accessible to the user via DataMirror. However, using these reflection APIs or calling .toDefinition will fully close a module, to ensure that subsequent boring fails (and thus getting all ports is never stale).
  Added a skipPrefix to enable ignoring the last prefix value in the prefix name stack.
• API for probing internal signals (by @debs-sifive in #3088)
  Adds an API for probing internal signals.
• Add ClockGate intrinsic (by @fabianschuiki in #3209)
  Add support for the circt.clock_gate intrinsic.
• Added more Connectable customization functions (by @azidar in #3227)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
  • Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
  • Added .as, a useful function on Connectable when users to upcast the Scala type.
  • Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (by @seldridge in #3181)
• [feature] Add properties to Interface (by @seldridge in #3238)
• Enable .viewAsSupertype to work on Records (by @mwachs5 in #3267)
  • Allow .viewAsSupertype to work on Records, with additional tests.
  • Ensure that errors in DataView show the problematic fields in a deterministic order.
• Add Top-level parameterized reset type (by @mwachs5 in #3276)
  Add a HasParameterizedResetType to mix into Modules for their top level .reset
• Allow out-of-package svsim backend implementations (by @GeorgeLyon in #3306)
  • Allow users of chisel to specify their own svsim.Backend implementations outside of Chisel. This is useful since in-tree backends may not support all versions of the specified backend (and we don't necessarily want them to).
• Support ref types on interfaces (by @trilorez in #3301)
• Fix color emission to check for interactive terminal (by @jackkoenig in #3334)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Unify recursive Data traversals into DataMirror (by @jared-barocsi in #3300)
• Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (by @jackkoenig in #3349)
• Add support for zero-width bit extraction (by @jackkoenig in #3352)
• Add basic linear temporal logic assertions (by @fabianschuiki in #3337)
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (by @jared-barocsi in #3228)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• Make it possible to illegalize .asUInt on OpaqueTypes (by @jackkoenig in #3344)
  Subclasses of OpaqueType can override errorOnAsUInt to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.
• Add MuxCell intrinsics (by @uenoku in #3372)
  This commit adds new intrinsics (MuxCell2 and MuxCell4) to provide users a way to directly use 2-to-1 and 4-to-1 MUX cells in synthesis tools (currently synopsys and cadence are supported) from Chisel level. Appropriate pragmas will be annotated in output verilog. FIRRTL implementation is llvm/circt#5428
• SRAM API: Add a parameter to initialize the memory (by @jared-barocsi in #3364)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (by @jackkoenig in #3389)
• SRAM API: Add multiple-clocked port API (by @jared-barocsi in #3383)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add a new take method on Bits that returns the requested number (by @chick in #3402)
  take will accept an argument of zero and will return a zero-length UInt
• Add support for configurable warnings (by @jackkoenig in #3414)
  Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
• Support leading whitespace in --warn-conf-file (by @jackkoenig in #3438)
  • Also make line comments work on lines with filter-action pairs.
• Add FirtoolBinaryPath option (by @GeorgeLyon in #3434)
  • Add FirtoolBinaryPathOption to select a different firtool binary at runtime.
• Add --dump-fir option to ChiselStage (by @jackkoenig in #3453)
  This option will dump the .fir before invoking firtool.
  • Additional changes:
    • Use os.lib for invoking firtool
    • Use lazy serialization to avoid holding the entire FIRRTL in memory.
    • Mix NoStackTrace into FirtoolNotFound
    • Fix detection of no firtool
• Add hook to invoke hardware generators at the end of elaboration. (by @mikeurbach in #3446)
• Initial properties package and Property type. (by @mikeurbach in #3425)
• Add support for Integer properties and conversion to FIRRTL. (by @mikeurbach in #3470)
  The Integer property type is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Support connecting Properties. (by @mikeurbach in #3481)
  Property assignment is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for Property literals, starting with existing int types. (by @mikeurbach in #3482)
  Property literals are defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for String Property type and literal. (by @mikeurbach in #3490)
• Add support for sequences of Properties, including values. (by @jackkoenig in #3491)
• Add support for Class and Object on top of Properties. (by @mikeurbach in #3489)
• Support Optionality of implicit clock and reset (by @jackkoenig in #3496)
  • withClock, withReset, and withClockAndReset now have forms that take Option[Clock] and Option[Reset]
  • Module.clockOption and Module.resetOption return Option[Clock] and Option[Reset]
• Add Boolean Property type (by @adkian-sifive in #3503)
  API Modification: Add Boolean support to Property API
• Implement CIRCT converter (by @SpriteOvO in #3466)
• Add Disable, a new API for disabling simulation constructs (by @jackkoenig in #3497)
  Disable is a new type that represents the concept of disabling a simulation construct. It is handled similarly to the implicit clock and reset except Disable is notionally a function ...

Chisel v6.0.0-RC2

Features

• Add ModuleChoice and Groups (by @nandor in #3683)
  Added support for the post-generation configuration of designs. Instance choices allow multiple, option-dependent targets to be specified for a single option, picking an implementation in the downstream flow.
• make SRAM targets accessible from SRAMInterface (by @debs-sifive in #3728)
  Makes SRAM targets accessible from SRAMInterfaces instantiated via the SRAM object, which sets the underlying field in SRAMInterface.

API Modification

• Promote FlatIO to package chisel3 (by @jackkoenig in #3727)
• Make chisel3.internal.firrtl.* private (by @jackkoenig in #3732)
  • Width, KnownWidth, and Unknown width promoted to package chisel3
  • Other classes moved to new package private chisel3.internal.firrtl.ir
• Delete many old deprecated APIs (by @jackkoenig in #3733)
  • trait AutoCloneType (its always enabled, the trait is a no-op)
  • chisel3.experimental.ChiselEnum (use chisel3.ChiselEnum)
  • chisel3.experimental.EnumType (use chisel3.EnumType)
  • chisel3.experimental.EnumType (use chisel3.reflect.DataMirror)
  • chisel3.internal.requireIsHardware (use chisel3.experimental.requireIsHardware)
  • chisel3.internal.requireIsChiselType (use chisel3.experimental.requireIsChiselType)
  • chisel3.internal.sourceinfo.* (use chisel3.experimental.sourceinfo.*)
  • chisel3.internal.prefix (use chisel3.experimental.prefix)
  • chisel3.internal.noPrefix (use chisel3.experimental.noPrefix)
  • chisel3.internal.ChiselException (use chisel3.ChiselException)
  • chisel3.internal.InstanceId (use chisel3.InstanceId)
  • trait BackendCompilationUtilities
  • chisel3.util.MuxLookup(key, default, mapping) (use chisel3.util.MuxLookup(key, default)(mapping), it has much better type inferencing behavior)
• Clean up Bindings deprecations (by @jackkoenig in #3736)
  • Make already deprecated APIs package private
  • Add deprecation warnings to a few that we missed

Performance

• Share the globalNamespace in the DynamicContext used for Definition. (by @mikeurbach in #3700)
  When creating large numbers of Definitions, copying the globalNamespace back and forth becomes a performance bottleneck.

Fixes

• Define typeEquivalent specially for Property. (by @mikeurbach in #3685)
  When we changed Property to extend Element, we needed to update some internal logic that checked "are these Elements the same type". That logic needs to work a little differently for Property, and this internal API is one other place that needed to be updated.
• dontTouch: Skip probe and properties. (by @dtzSiFive in #3691)
• Fix the --mlir-print-ir-after-all option. (by @poemonsense in #3704)
  Fix the --mlir-print-ir-after-all option.
• Fix using Definitions as arguments to Definitions (by @jackkoenig in #3726)
  Fixes #3708

Documentation

• [docs] Fix release ordering and make RC count as latest (by @jackkoenig in #3686)
• [docs] update firtool version (by @schoeberl in #3670)
• [docs] Add Firtool versions table to Versioning page (by @jackkoenig in #3694)
  This table is generated for all versions of Chisel that include BuildInfo.firtoolVersion and will thus automatically include new releases. Versions of Chisel that predate BuildInfo.firtoolVersion are included in the table manually.
• [docs] Fix links from ScalaDoc to source code (by @jackkoenig in #3697)
• Add riscvassembler lib to community projects (by @carlosedp in #3717)
  Added RISCVAssembler Scala library to community projects.

Dependency Updates

• Bump firtool-resolver to 1.1.0 (by @jackkoenig in #3696)
  The logic for
  • If FIRTOOL_PATH is set, the --version regex failing no longer will return fail, instead it will set version to <unknown>.
  • If FIRTOOL_PATH is set and something fails (firtool not found or cannot execute the binary), then the error will be returned rather than firtool-resolver falling back to fetching the default version.
  • Errors from running firtool will be logged and returned rather than unconditionally turned into "Firtool binary not on FIRTOOL_PATH".
• Bump firtool resolver to 1.2.0 (by @jackkoenig in #3702)
  Now it will fetch llvm-firtool with classifier for the current system rather than the full artifact which contains binaries for all platforms.
• Bump firtool-resolver to 1.3.0 (by @jackkoenig in #3719)
  To override which firtool is used by Chisel, users can set environment variable CHISEL_FIRTOOL_PATH.
• [cd] Bump CIRCT from firtool-1.61.0 to firtool-1.62.0 (by @chiselbot in #3725)

Build and Internal Changes

• fix up path issue in build.sc (by @sequencer in #3692)
• Fix publish (by @jackkoenig in #3695)
• [CI] Fix flaky CI and remove VerilogMdocModifier from API docs (by @jackkoenig in #3701)
  • Use Java 17 to build documentation in CI

• Exclude docs project from Unidoc

• bump and update nix to use upstreamed packages (by @sequencer in #3713)
• [CI] Fix CI flakiness with --server=false (by @jackkoenig in #3722)
• Bump SBT to 1.9.8 and update Ubuntu runners (by @jackkoenig in #3734)

Full Changelog: v6.0.0-RC1...v6.0.0-RC2

Chisel v6.0.0-RC1

Features

• Add Map properties (by @albertchen-sifive in #3505)
• add Double property type (by @albertchen-sifive in #3508)
• add Path property type (by @albertchen-sifive in #3511)
• add DedupGroupAnnotation (by @albertchen-sifive in #3500)
• add tuple properties (by @albertchen-sifive in #3513)
• Map Properties now support Properties as the key (by @jackkoenig in #3518)
• make PropertyType public, add Path factory method (by @albertchen-sifive in #3516)
• Add AnyRef type and rework PropertyType.getPropertyType (by @albertchen-sifive in #3522)
• Implement FIRRTL type alias mechanism for Bundles (by @jared-barocsi in #3445)
  Add aliasName to Bundles: a way for users to define a type alias for a bundle type, resulting in the emission and usage of alias type statements in FIRRTL.
• Implement auto typeName generation for Records (by @jared-barocsi in #3504)
  Add experimental HasAutoTypename trait
• Allows users to automatically generate a typeName for Bundle objects through the compiler plugin.
• Make FlatIO work (as IO) for non-Record Data (by @seldridge in #3538)
• Add FixedIORawModule, FixedIOBlackBox (by @seldridge in #3535)
• Add optional group API (by @seldridge in #3541)
• Add DedupGroupAnnotation phase (by @adkian-sifive in #3545)
  Add DedupGroupAnnotation phase that generates deduplication groups based on module desiredNames
• Support probe-define in monoconnects (by @rwy7 in #3566)
  • Enable mono/ :=connects for probes, which will emit a ProbeDefine.
• Also enables the fancier connect forms
• A "Probe" will be connected at the root
• Add new target API to get a target relative to a specific BaseModule. (by @mikeurbach in #3581)
  The new toRelativeTarget API augments the existing toAbsoluteTarget API, to provide a mechanism to get hierarchical paths to a NamedComponent relative to a known root.
• Support wire-of-probe. (by @dtzSiFive in #3592)
  Allow creation of wire of probe, not in specification but supported by CIRCT.
• Added disallowIOCreation as a public API (by @azidar in #3575)
  Enable users to lock-down the IO-creation of any module by calling disallowIOCreation(). This is useful for building chisel libraries which desire this behavior, but don't want to force a user to declare the entire IO in one bundle.
• Support instanceName on HasId without a component by using localName. (by @mikeurbach in #3623)
  We have recently reworked when HasIds are named within a module so they can be named before atModuleBodyEnd executes, and then get referenced within atModuleBodyEnd. However, the component is still not set when they are referenced, so in this case use the local name.
• Add source locators to all subclasses of BaseModule (by @jackkoenig in #3624)
  The source locators point to the name of the class extends Module, RawModule, BlackBox, ExtModule, or Class. They are included in the output FIRRTL.
• Add SparseVec (by @seldridge in #3619)
• Support Instance for Definitions of Classes. (by @mikeurbach in #3628)
  This allows safe references to Objects, as well as type-safe field accessors to connect inputs or outputs via @instantiable and @pulic.
• DataMirror.isFullyAligned: add method to check data is all aligned. (by @dtzSiFive in #3613)
  Add new DataMirror.isFullyAligned for checking if all members are aligned w.r.t. the given base.
• dontTouch should default to leaf marking rather than aggregate marking to match current behavior (by @darthscsi in #3675)
  Don't touch is becoming stricter. Specifically type lowering and don't touch of aggregates are in conflict. dontTouch will maintain the same behavior by default by applying dontTouch to every leaf when the argument is an Aggregate. The new argument markAgg can be set to true to have dontTouch mark the Aggregate instead.

API Modification

• Property now extends Data, remove BaseType (by @jackkoenig in #3514)
  Properties can be fields of Bundles and used in wires.
• MixedVec subclasses immutable.IndexedSeq (by @mwachs5 in #3539)
  Change MixedVec to inherit from collection.immutable.IndexedSeq, so that it can work for Seq[Data].
• remove clock and cond from probe force/release API (by @debs-sifive in #3605)
  Remove clock and cond from probe force and release methods.
• Remove Map and Tuple property types. (by @mikeurbach in #3627)
  These property types weren't necessary in the end. A Map can easily be represented by a list of object with two fields, and this is how it's been done downstream. Similarly, a Tuple can easily be represented by an object with two fields, and this is how it's been done downstream. Remove these to simplify Chisel and reduce maintainence burden.
• Rename "groups" to "layers" (by @seldridge in #3632)
• Make SRAM ports public (by @debs-sifive in #3652)
  Make MemoryWritePort and MemoryReadWritePort classes publicly accessible.

Backend Code Generation

• Aggregate literals now materialize const wires (by @trilorez in #3515)
  Aggregate literals now materialize const wires. This will facilitate further support for const in operations and the type system in the future.
• firrtl: Emit under 3.2.0 (not released) to cover property features. (by @dtzSiFive in #3517)
  Bump FIRRTL version to unreleased 3.2.0 to cover experimental features emitted.
• Additional checks in probe packagae (by @debs-sifive in #3610)
  Error instead of emitting RW/ProbeValues on literals.
• Don't emit nodes when calling .asBool on a Bool (by @jackkoenig in #3637)
  This results in a slight improvement to emitted FIRRTL quality

Fixes

• Allow properties on ExtModule IO (by @seldridge in #3510)
• Improve error messages involving views (by @jackkoenig in #3536)
  This improves error messages involving views where the view maps to a single Data. The error messages on legacy connections (:= and <>) involving views that do not correspond 1-1 with a single target Data are still bad, but connectables (eg. :#=) do benefit even in that case.
• [Binder] Corrent chirrtl.memoryport position (by @SpriteOvO in #3544)
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (by @jackkoenig in #3553)
• Partial fix for probe and Decoupled interaction + demo of workaround (by @debs-sifive in #3558)
  Coerces tapAndRead to punch stripped-direction flips when punching downwards with Inward non-probe ports, Fixes #3556
• Fix 'Malformed class name' errors in typeName and related implementations (by @jared-barocsi in #3533)
  • Introduce a simpleClassName utility object that emulates a getClass.getSimpleName call without throwing Malformed class name exceptions when Java 8 is used. typeName and all related implementations use this function now instead of getClass.getSimpleName.
• HasAutoTypename can no longer be mixed into an anonymous Record; the compiler plugin now reports this as a compilation error.
• Fix and test probe of ChiselEnum. (by @dtzSiFive in #3560)
  Fix probe of ChiselEnum.
• Fix BoringUtils.bore can not bore from a Probe (by @sequencer in #3512)
• Fix Decodetable (by @sequencer in #3563)
• Don't add DedupGroupAnnotation to intrinsics (by @mikeurbach in #3590)
• Bugfix: foo and foo_ names cause incorrect prefix calculation (by @azidar in #3600)
  Naming foo and then foo_ will no longer trigger an error.
• Don't add DedupGroupAnnotation to classes. (by @mikeurbach in #3604)
  Class definition components cannot have any annotations.
• Updated Path property target type serialization. (by @mikeurbach in #3601)
  This includes two changes to how Path property target types are serialized:

• For ModuleTargets, use the OMInstanceTarget target type, like for InstanceTargets
• Add a new API to request "member" target types

• set sample_element's probeInfo for Vecs (by @debs-sifive in #3611)
  For Vecs, also set the probeInfo of their sample_element, which is used to determine ...

Chisel v5.1.0

Features

• Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in #3336)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
  • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
  • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (backport #3349) (by @mergify[bot] in #3351)
• Add support for zero-width bit extraction (backport #3352) (by @mergify[bot] in #3354)
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in #3362)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in #3380)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in #3391)
• SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in #3405)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add support for configurable warnings (backport #3414) (by @mergify[bot] in #3431)
  Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
• Enrich ShiftRegister with SyncReadMem-based implementation. (backport #2891) (by @mergify[bot] in #3571)
  Supplement ShiftRegister with SyncReadMem-based implementation.
• Add --dump-fir option to ChiselStage (backport #3453) (by @mergify[bot] in #3456)
  This option will dump the .fir before invoking firtool.
  • Additional changes:
    • Use os.lib for invoking firtool
    • Use lazy serialization to avoid holding the entire FIRRTL in memory.
    • Mix NoStackTrace into FirtoolNotFound
    • Fix detection of no firtool

API Deprecation

• Deprecate calling .viewAs on non-hardware (backport #3395) (by @mergify[bot] in #3400)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Performance

• Convert Vec dynamic index with a literal to static index (backport #3314) (by @mergify[bot] in #3319)
• Fix issue where reify would do the same lookup twice (backport #3392) (by @mergify[bot] in #3397)
• Optimize source locator escaping when emitting FIRRTL (backport #3439) (by @mergify[bot] in #3449)
  Only escape/unescape source locators that need it, avoids a String copy in the common case.

Fixes

• Gate sys/personality.h include under define (backport #3307) (by @mergify[bot] in #3308)
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in #3316)
• Make svsim shutdown gracefully when the test throws an exception (backport #3309) (by @mergify[bot] in #3310)
  • Fixed an issue where throwing an assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.
• Report Builder errors even when exception is thrown (backport #3341) (by @mergify[bot] in #3343)
  Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Add messages to require statements in Math (backport #3385) (by @mergify[bot] in #3388)
  • log2 functions
  • unsignedBitLength
• [svsim] Don't redirect simulation stderr to a pipe (backport #3403) (by @mergify[bot] in #3406)
  • Fixes an issue where simulations that logged to stderr could hang
• Sanitize Record._elements (backport #3419) (by @mergify[bot] in #3427)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Restore BundleUpcastable (backport #3487) (by @mergify[bot] in #3494)
  Restore BundleUpcastable and deprecate it.
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #3553) (by @mergify[bot] in #3555)
• Fix Decodetable (backport #3563) (by @mergify[bot] in #3580)
• Add type ascription to implicits from instantiable (backport #3615) (by @mergify[bot] in #3618)
  This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.

Documentation

• Remove references to interval types from the website docs (backport #3345) (by @mergify[bot] in #3348)
  Fixes #3325
• Bring ToC and Menu into alignment, some minor cleanup within docs (backport #3346) (by @mergify[bot] in #3347)
  Fix #3322
• Changed Array to Seq in MuxLookup explantation (backport #3547) (by @mergify[bot] in #3550)

Dependency Updates

• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (backport #3327) (by @mergify[bot] in #3330)
• Bump to firtool 1.43.0 (backport #3332) (by @mergify[bot] in #3333)
  See release notes for firtool 1.41.0, 1.42.0, and 1.43.0.
• Add support for Scala 2.13.12 to the compiler plugin (backport #3527) (by @mergify[bot] in #3530)

Build and Internal Changes

• [5.x] Enable MiMa for v5.0.0 (by @chiselbot in #3290)
• [CI] Update versions in CI Workflow (backport #3291) (by @mergify[bot] in #3292)
• upgrade mill to 0.11.0 (backport #3367) (by @mergify[bot] in #3407)

Full Changelog: v5.0.0...v5.1.0

Chisel v6.0.0-M3

Features

• Make it possible to illegalize .asUInt on OpaqueTypes (by @jackkoenig in #3344)
  Subclasses of OpaqueType can override errorOnAsUInt to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.
• Add MuxCell intrinsics (by @uenoku in #3372)
  This commit adds new intrinsics (MuxCell2 and MuxCell4) to provide users a way to directly use 2-to-1 and 4-to-1 MUX cells in synthesis tools (currently synopsys and cadence are supported) from Chisel level. Appropriate pragmas will be annotated in output verilog. FIRRTL implementation is llvm/circt#5428
• SRAM API: Add a parameter to initialize the memory (by @jared-barocsi in #3364)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (by @jackkoenig in #3389)
• SRAM API: Add multiple-clocked port API (by @jared-barocsi in #3383)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add a new take method on Bits that returns the requested number (by @chick in #3402)
  take will accept an argument of zero and will return a zero-length UInt
• Add support for configurable warnings (by @jackkoenig in #3414)
  Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
• Support leading whitespace in --warn-conf-file (by @jackkoenig in #3438)
  • Also make line comments work on lines with filter-action pairs.
• Add FirtoolBinaryPath option (by @GeorgeLyon in #3434)
  • Add FirtoolBinaryPathOption to select a different firtool binary at runtime.
• Add --dump-fir option to ChiselStage (by @jackkoenig in #3453)
  This option will dump the .fir before invoking firtool.

• Additional changes:
  • Use os.lib for invoking firtool
  • Use lazy serialization to avoid holding the entire FIRRTL in memory.
  • Mix NoStackTrace into FirtoolNotFound
  • Fix detection of no firtool

• Add hook to invoke hardware generators at the end of elaboration. (by @mikeurbach in #3446)
• Initial properties package and Property type. (by @mikeurbach in #3425)
• Add support for Integer properties and conversion to FIRRTL. (by @mikeurbach in #3470)
  The Integer property type is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Support connecting Properties. (by @mikeurbach in #3481)
  Property assignment is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for Property literals, starting with existing int types. (by @mikeurbach in #3482)
  Property literals are defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for String Property type and literal. (by @mikeurbach in #3490)
• Add support for sequences of Properties, including values. (by @jackkoenig in #3491)
• Add support for Class and Object on top of Properties. (by @mikeurbach in #3489)
• Support Optionality of implicit clock and reset (by @jackkoenig in #3496)
  • withClock, withReset, and withClockAndReset now have forms that take Option[Clock] and Option[Reset]

• Module.clockOption and Module.resetOption return Option[Clock] and Option[Reset]

• Add Boolean Property type (by @adkian-sifive in #3503)
  API Modification: Add Boolean support to Property API
• Implement CIRCT converter (by @SpriteOvO in #3466)
• Add Disable, a new API for disabling simulation constructs (by @jackkoenig in #3497)
  Disable is a new type that represents the concept of disabling a simulation construct. It is handled similarly to the implicit clock and reset except Disable is notionally a function of the current implicit reset. Its default value is "not has been reset", a two-state simulation-only construct that is 0 when simulation starts and only becomes 1 after reset has been asserted, and then de-asserted. Because Disable has simulation-only semantics, it is not a Data and can only be used by simulation-only APIs.

API Modification

• Error when calling .viewAs on non-hardware (by @jackkoenig in #3398)
• Add a new BaseType type that Data inherits, and use it for ports. (by @mikeurbach in #3429)
• Make LTL properties use Clock and Disable by default (by @jackkoenig in #3498)
  Properties in package chisel3.ltl will now be clocked and disabled by default (if there is an implicit clock and disable). Default disable is not hasBeenReset of the current implicit reset (if one exists). The clock and disable can be removed by setting them to None via withClock, withReset, and withDisable APIs.

API Deprecation

• Deprecate calling .viewAs on non-hardware (by @jackkoenig in #3395)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.
• Deprecate old BoringUtils API (by @jared-barocsi in #3428)
  BoringUtils.bore(source, sinks), BoringUtils.addSource and BoringUtils.addSink are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source), BoringUtils.tap(source) ...

Backend Code Generation

• [codegen] Use FIRRTL 3.0.0 syntax (connect, invalidate, regreset, radix-encoded integer literals) (by @seldridge in #3188)
• [codegen] Emit literal identifiers for numeric ids (by @seldridge in #3374)
  Use FIRRTL 3.0.0 emission of literal identifiers when a Chisel name begins with a digit.
• Support bulk connection for const types (by @trilorez in #3384)
• Avoid emitting 'const const' for const vecs of const elements (by @trilorez in #3393)
  Multiple consecutive 'const' modifiers are no longer emitted when emitting a const vector of const elements.
• Update BoringUtils.bore to not add a port when boring from a port. (by @mikeurbach in #3411)
• update ChiselPlugin to name tuples (by @albertchen-sifive in #3436)
  The chisel plugin will now name wires that are part of tuples e.g. val x = (Wire(Bool()), Wire(Bool())) will generate wires with names x_1 and x_2

Performance

• Fix issue where reify would do the same lookup twice (by @jackkoenig in #3392)
• Optimize source locator escaping when emitting FIRRTL (by @jackkoenig in #3439)
  Only escape/unescape source locators that need it, avoids a String copy in the common case.
• Use Instantiate for LTL intrinsic instantiation (by @jackkoenig in #3499)
  This vastly reduces the IR size when using LTL properties

Fixes

• Correctly set ProbeInfo to None for Aggregate types on a probe.read (by @girishpai in #3382)
  Probe.read needs to return non-probe data to work with connection operators. Previous version of this was not handling aggregates correctly - this PR rectifies that.
• Add messages to require statements in Math (by @jackkoenig in #3385)
  • log2 functions
  • unsignedBitLength
• [svsim] Don't redirect simulation stderr to a pipe (by @GeorgeLyon in #3403)
  • Fixes an issue where simulations that logged to stderr could hang
• Sanitize Record._elements (by @jackkoenig in #3419)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Extend constants in probe.force and probe.forceInitial methods. (by @debs-sifive in #3418)
  Properly extend forced values in probe.force and probe.forceInitial methods. Error out on unknown widths.
• Remove SourceLineNoCol (by @jackkoenig in #3433)
  Tweak emission of source locators in error messages to match format in emitting FIRRTL (removed the : between filename and line number).
• Remove intermediate wire creation from Boringutils Tap API (by @debs-sifive in #3441)
  Remove intermediate wire creation from...

Chisel v6.0.0-M2

Features

• Add Top-level parameterized reset type (by @mwachs5 in #3276)
  Add a HasParameterizedResetType to mix into Modules for their top level .reset
• Allow out-of-package svsim backend implementations (by @GeorgeLyon in #3306)
  • Allow users of chisel to specify their own svsim.Backend implementations outside of Chisel. This is useful since in-tree backends may not support all versions of the specified backend (and we don't necessarily want them to).
• Support ref types on interfaces (by @trilorez in #3301)
• Fix color emission to check for interactive terminal (by @jackkoenig in #3334)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
  • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
  • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Unify recursive Data traversals into DataMirror (by @jared-barocsi in #3300)
• Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (by @jackkoenig in #3349)
• Add support for zero-width bit extraction (by @jackkoenig in #3352)
• Add basic linear temporal logic assertions (by @fabianschuiki in #3337)
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (by @jared-barocsi in #3228)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.

API Modification

• Create "tap" API for boring probe-type (non-synthesizable) ports (by @debs-sifive in #3237)
  Create "tap" API for boring probe-type (non-synthesizable) ports.
• BoringUtils writable tap (rwTap) API (by @debs-sifive in #3284)
  Add writable tap (rwTap) API to BoringUtils, which drills writable probe ports downwards only.
• Remove support for Scala 2.12 (by @jackkoenig in #3331)
  Chisel 5 was the last major version supporting Scala 2.12, please upgrade to Scala 2.13.

API Deprecation

• Warn on incorrect widths for Vec dynamic indexing (by @jackkoenig in #3321)

Backend Code Generation

• [codegen] Simpler FIRRTL Code for Reg w/o Reset (by @seldridge in #3280)

Performance

• Optimize BitPat equals, overlap, and cover (by @jackkoenig in #3285)
• Convert Vec dynamic index with a literal to static index (by @jackkoenig in #3314)

Fixes

• Gate sys/personality.h include under define (by @trilorez in #3307)
• Make svsim shutdown gracefully when the test throws an exception (by @GeorgeLyon in #3309)
  • Fixed an issue where throwing an assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (by @jared-barocsi in #3313)
• Report Builder errors even when exception is thrown (by @jackkoenig in #3341)
  Chisel will report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Support linking ref types on interfaces (by @trilorez in #3326)

Documentation

• [docs] Update website for 5.0, 6.0 and fix links (by @jackkoenig in #3274)
• Update roadmap. (by @gonsolo in #3295)
• Bring ToC and Menu into alignment, some minor cleanup within docs (by @mwachs5 in #3346)
  Fix #3322
• Remove references to interval types from the website docs (by @mwachs5 in #3345)
  Fixes #3325
• Update meeting time and versions in README (by @jackkoenig in #3356)

Dependency Updates

• Update scalacheck-1-15 to 3.2.14.0 (by @scala-steward in #3265)
• Update scalatest to 3.2.16 (by @scala-steward in #3299)
• Update sbt to 1.8.3 (by @scala-steward in #3298)
• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (by @jackkoenig in #3327)
• Bump to firtool 1.43.0 (by @jackkoenig in #3332)
  See release notes for firtool 1.41.0, 1.42.0, and 1.43.0.
• Bump to Scala 2.13.11 (by @jackkoenig in #3358)

Build and Internal Changes

• SemanticDB requires private fields of case class to use "val" (by @jackkoenig in #3270)
• Update PULL_REQUEST_TEMPLATE.md (by @mwachs5 in #3279)
  Update PR template to be less comment-driven
• [CI] Update versions in CI Workflow (by @jackkoenig in #3291)
• Update ChiselRunners to use svsim (by @GeorgeLyon in #3147)
  • All ChiselRunner tests now use svsim when calling assertTester{Passes,Fails}
• Add tests for using DataView with ref types (by @trilorez in #3320)
• Update sbt to 1.9.0 (by @scala-steward in #3339)
• Update sbt-scalafix to 0.11.0 (by @scala-steward in #3338)
• Make devcontainer point to CIRCT top-of-tree instead of latest release (by @GeorgeLyon in #3360)
  • VSCode devcontainer now follows CIRCT top-of-tree rather than latest release

Full Changelog: v6.0.0-M1...v6.0.0-M2

Chisel v5.0.0

Features

• add MuxLookup.fromEnum (by @albertchen-sifive in #3071)
  add chisel3.util.MuxLookup.fromEnum
• Fix FIRRTL spec emission and bump to spec 1.2.0 (by @jackkoenig in #3094)
  Fix emission of FIRRTL spec in emitted .fir. Now emitting FIRRTL version 1.2.0.
• add curried MuxLookup.apply, deprecate old apply (by @albertchen-sifive in #3095)
  Add a new version of MuxLookup.apply that takes two parameter lists instead of one. This helps the scala compiler report better type errors.
• Introduce svsim, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in #3121)
  Added svsim, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.
• Add Simulator class for simulating Chisel modules with svsim (by @GeorgeLyon in #3136)
  • Added chisel3.simulator.Simulator for simulating Chisel modules with svsim
• Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
• Add EphemeralSimulator API (by @GeorgeLyon in #3142)
  • Introduce chisel3.simulator.EphemeralSimulator for ephemeral scenarios (such as scala-cli)
• [svsim] Add option to wait for a VCS license if one is unavailable (by @GeorgeLyon in #3149)
• intmodule exporting (by @darthscsi in #3148)
  Generate implementation-specific intirnsics.
• Implement typeName API for stable Module names (by @jared-barocsi in #3130)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues
• More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue) (by @darthscsi in #2958)
  Add support for Circt intrinsics.
• Added .exclude to Connectable (by @azidar in #3172)
  Added .exclude mechanism on Connectable to enable never connecting to/from the marked fields using any connectable operator.
• Add an annotation for specifying module port conventions (by @rwy7 in #3030)
• Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (by @jared-barocsi in #3171)
  Fix VecInit.fill(0) calls so that they compile and yield 0-width Vecs
• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3214)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• Added more Connectable customization functions (backport #3227) (by @mergify[bot] in #3231)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
• Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
• Added .as, a useful function on Connectable when users to upcast the Scala type.
• Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in #3259)
• Enable .viewAsSupertype to work on Records (backport #3267) (by @mergify[bot] in #3269)
  • Allow .viewAsSupertype to work on Records, with additional tests.

• Ensure that errors in DataView show the problematic fields in a deterministic order.

• Add Top-level parameterized reset type (backport #3276) (by @mergify[bot] in #3282)
  Add a HasParameterizedResetType to mix into Modules for their top level .reset

API Modification

• [chisel5] git subtree add FIRRTL (by @seldridge in #2982)
• [chisel5] Build FIRRTL in-tree, not published dependency (by @seldridge in #2983)
• [chisel5] Remove SFC Compiler from FIRRTL Subtree (by @seldridge in #2984)
• Removed innards and NotStrict for CompileOptions, and object Chisel (by @azidar in #3055)
  Removal of Chisel and the NotStrict compile options.
• Remove compile options everywhere in Chisel internals. (by @azidar in #3056)
  Removed CompileOptions trait and associated code, as it is now unnecessary.
• Remove LegacyModule and LegacyBlackBox (by @azidar in #3058)
  Removed LegacyModule and LegacyBlackBox. Users should instead now extend Module or BlackBox.
• [nfc] Remove two unused SFC annotations (by @seldridge in #3102)
• Remove ImplicitInvalidate (by @azidar in #3096)
  Remove ImplicitInvalidate - now users must explicitly assign DontCare to a module, at instantiation site, rather than this happening automatically because the module extended ImplicitInvalidate.
• Remove reflectivelyFindIO, its unused (by @azidar in #3106)
• Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
• Fix Printf macro to catch s-interpolator usages in Scala 2.13 (by @adkian-sifive in #3143)
  Fix issue with printf macro error checking to catch s-interpolator usages in Scala 2.13
• Remove _compatAutoWrapPorts no-op method (by @seldridge in #3164)
• Emit annotations in the .fir file (by @jackkoenig in #3180)
  • Annotations are now emitted in the .fir file instead of in an auxiliary .anno.json file.
  • Serialized FIRRTL is now spec v2.0.0

API Deprecation

• Deprecate ChiselStage$.elaborate (by @seldridge in #3160)
• Deprecate Scala 2.12 in Chisel 3.6 through the compiler plugin (by @jared-barocsi in #3146)
  Deprecate Scala 2.12 for Chisel 3.6 and later versions

Performance

• Make return value of Serializer.lazily lazy (by @jackkoenig in #3122)
  Reduce peak memory usage during .fir serialization by using lazy intermediate data structures.
• Optimize BitPat equals, overlap, and cover (backport #3285) (by @mergify[bot] in #3288)

Fixes

• Fix paper cut: bad message on calling litValue on Bundle containing DontCare (by @chick in #3043)
  There is now a better message when calling litValue on a Bundle that contains a DontCare
  that shows the Bundle and fields
• Disallow --target-dir in ChiselStage$ (by @seldridge in #3063)
• Remove deprecated CIRCT Options (by @seldridge in #3101)
• Detect bound hardware when processing record elements (by @adkian-sifive in #3037)
  Using bound hardware as an Element for a Record will now throw a better error message
• Actually fail on compilation errors and fix issue with older gcc versions (by @GeorgeLyon in #3132)
• Fix naming for RHS of named unapply expressions (by @jackkoenig in #3163)
  This results in previously unnamed signals receiving names from the compiler plugin.
• Report firtool version when firtool invocation errors (by @jackkoenig in #3174)
• Revert checks for size 0 Vecs in connections (backport #3215) (by @mergify[bot] in #3216)
• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3218)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.

Documentation

• Fix broken cookbook link (by @mwachs5 in #3073)
  Fix broken link in the cookbook about resolving UInt index mismatches
• Update README, fix link to roadmap.md (by @jensengrey in #3091)
• Update README.md, fix scala version support badge (by @seanjensengrey in #3119)
• mdoc-ify intrinsic explanation (by @mwachs5 in #3152)
  Use mdoc to compile check the intrinsics explanation doc
• update website and explanations menus to match eachother (by @mwachs5 in #3154)
  [Website] Update Explanation Menus to align with eachother
• Fix three broken links in README.md Documentation section (by @aswaterman in #3166)
• [CI] Add Release Notes Automation (by @jackkoenig in #3170)
• Update README.md for Chisel 5 (by @jackkoenig in https://github.com/c...

Chisel v6.0.0-M1

Features

• Add ConstType and Const(...) API (by @debs-sifive in #3046)
  Adds Const() API to create ConstTypes, which denotes Data that holds a constant value.
• Implement read-write memory accessors for SyncReadMem (by @jared-barocsi in #3190)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• [Feature] Add Interface, ConformsTo for Separate Compilation (by @seldridge in #3199)
• Handle BoringUtils in Chisel, rather than in FIRRTL compiler (by @azidar in #3187)
  • Added a new BoringUtils.bore that is performed during Chisel elaboration, not via Annotations+CIRCT. Punched ports are accessible to the user via DataMirror. However, using these reflection APIs or calling .toDefinition will fully close a module, to ensure that subsequent boring fails (and thus getting all ports is never stale).
  • Added a skipPrefix to enable ignoring the last prefix value in the prefix name stack.
• API for probing internal signals (by @debs-sifive in #3088)
  Adds an API for probing internal signals.
• Add ClockGate intrinsic (by @fabianschuiki in #3209)
  Add support for the circt.clock_gate intrinsic.
• Added more Connectable customization functions (by @azidar in #3227)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
• Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
• Added .as, a useful function on Connectable when users to upcast the Scala type.
• Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (by @seldridge in #3181)
• [feature] Add properties to Interface (by @seldridge in #3238)
• Enable .viewAsSupertype to work on Records (by @mwachs5 in #3267)
  • Allow .viewAsSupertype to work on Records, with additional tests.

• Ensure that errors in DataView show the problematic fields in a deterministic order.

Fixes

• Revert checks for size 0 Vecs in connections (by @jackkoenig in #3215)
• Fix Instantiate for Product parameters (by @jackkoenig in #3210)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.
• [bugfix] Fix naming module with Unit parameter (by @seldridge in #3263)

Documentation

• [docs] Fix README logo and update versions (by @jackkoenig in #3189)
• [fix] typo fix: chosen port of arbiter is not onehot but UInt (by @SihaoLiu in #3235)
  Just a oneline fix to the comment of Arbiter chosen port

Dependency Updates

• Bump firtool version to 1.40.0 (by @seldridge in #3226)
• Update sbt-ci-release to 1.5.12 (by @scala-steward in #3234)
• Update sbt-mima-plugin to 1.1.2 (by @scala-steward in #3145)
• Update scalacheck-1-14 to 3.2.11.0 (by @scala-steward in #3264)
• Update data-class to 0.2.6 (by @scala-steward in #3049)
• Update sbt-assembly to 2.1.1 (by @scala-steward in #3047)
• Update scopt to 4.1.0 (by @scala-steward in #3048)
• Update upickle to 3.1.0 (by @scala-steward in #3169)

Build and Internal Changes

• Remove PartialConnect (by @seldridge in #3185)
• Update Mergify for backporting to 5.x (by @jackkoenig in #3191)
• Add Chisel Scala CLI template and automation (by @jackkoenig in #3186)
  Add a new Chisel template for using Chisel with Scala CLI, and adds some automation for uploading versions of this template on tagged releases (or workflow dispatch).
• Add Data.findFirstTypeMismatch for better type checking (by @jackkoenig in #3201)
• Read previousVersions for bincompat checking from a file (by @jackkoenig in #3202)
  We can now simply append versions as they are released to project/previous-versions.txt on relevant release branches. build.sbt also now contains instructions are how to waive binary compatibility breakages.
• Enable push CI on all *.x branches (by @jackkoenig in #3222)
• Improve SyncReadMem.read, .readWrite (by @jared-barocsi in #3221)
• Add workflow to automatically update binary compatibility checks (by @jackkoenig in #3242)
• Add new workflow to fixup backports for release notes (by @jackkoenig in #3252)
  Improve backport automation so that release notes generation from backport PRs works properly.
• Update .scala-steward.conf (by @jackkoenig in #3266)
  Make the frequency a legal value (14 days).

Full Changelog: v5.0.0-RC2...v6.0.0-M1

Chisel v5.0.0-RC2

Features

• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3214)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• Added more Connectable customization functions (backport #3227) (by @mergify[bot] in #3231)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
  • Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
  • Added .as, a useful function on Connectable when users to upcast the Scala type.
  • Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration

Fixes

• Revert checks for size 0 Vecs in connections (backport #3215) (by @mergify[bot] in #3216)
• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3218)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.

Documentation

• [docs] Fix README logo and update versions (backport #3189) (by @mergify[bot] in #3193)

Dependency Updates

• Bump firtool version to 1.40.0 (backport #3226) (by @mergify[bot] in #3229)

Build and Internal Changes

• Add Chisel Scala CLI template and automation (backport #3186) (by @mergify[bot] in #3194)
  Add a new Chisel template for using Chisel with Scala CLI, and adds some automation for uploading versions of this template on tagged releases (or workflow dispatch).
• Add Data.findFirstTypeMismatch for better type checking (backport #3201) (by @mergify[bot] in #3205)
• Read previousVersions for bincompat checking from a file (backport #3202) (by @mergify[bot] in #3208)
  We can now simply append versions as they are released to project/previous-versions.txt on relevant release branches. build.sbt also now contains instructions are how to waive binary compatibility breakages.
• Enable push CI on all *.x branches (backport #3222) (by @mergify[bot] in #3223)
• Improve SyncReadMem.read, .readWrite (backport #3221) (by @mergify[bot] in #3233)

Full Changelog: v5.0.0-RC1...v5.0.0-RC2