[WIP] [RISCV][SG2042] feat: add sg2042 support #399

RevySR · 2024-09-03T13:17:10Z

No description provided.

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

deepin-ci-robot · 2024-09-03T13:17:18Z

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Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

The standardized Zicbom extension supports only VA, however there's some vendor extensions (e.g. XtheadCmo) that can handle cache management operations on PA directly, bypassing the TLB lookup. Add a CMO alternatives macro variant that come with both VA and PA supplied, and the code can be patched to use either the VA or the PA at runtime. In this case the codepath is now patched to use VA for Zicbom and PA for XtheadCmo. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org>

DMA synchorization is done on PA and the VA is calculated from the PA. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org>

When doing DMA page preparation, both the VA and the PA are easily accessible from struct page. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

Originall the T-Head PBMT implementation in the kernel is intended for D1, thus the Sharable bit is not set. In addition, the Bufferable bit is not set for writecombine situation. Set these bits in the T-Head PBMT attributes definition. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

Fix qspinlock issue that loops to call cpu_relax and not exit. The call trace is: queued_spin_lock_slowpath->arch_mcs_spin_lock_contended ->smp_cond_load_acquire. RISCV has not defined smp_cond_load_acquire, so it uses generic funtion that defined in include/asm-generic/barrier.h. The generic smp_cond_load_acquire calls smp_cond_load_relaxed that loops to call READ_ONCE and cpu_relax. The READ_ONCE need barrier after it to get the new value.

Fix T-Head C9xx store merge buffer delay problem Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

Sophgo SPI Flash Master Controller (SPIFMC) is a master controller to control serial SPI Flash. Enable CONFIG_SPI_SOPHGO_SPIFMC if you have a device with a SPIFMC controller and want to access the Flash as a mtd device. There is GD25LB512ME Serial Flash on SG2042 EVB, controlled by SPIFMC. Signed-off-by: jingyu.li01 <jingyu.li01@sophgo.com>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

Signed-off-by: fengchun.li <fengchun.li@sophgo.com>

Turn on msi-x for top intr. Create msi-x whitelist, Limited the number of msi-x interrupts for inter x520 and wangxun NIC. Signed-off-by: chengjun.li <chengjun.li@sophgo.com>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

This is needed to support recent hardware in the amdgpu DRM driver. The FPU code in that driver is not performance-critical, so only provide the minimal support. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

Since it is not possible to incrementally add/remove extensions from the compiler's ISA string by appending arguments, any code that wants to modify the ISA string must recreate the whole thing. To support this, factor out the logic for generating the -march argument so it can be reused where needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other architectures. Enabling hardware FP requires overriding the ISA string for the relevant compilation units. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

refs: https://lore.kernel.org/lkml/f75c763d86529a47eb23d46c5ef9bcbaaf118200.1690274483.git.petr.tesarik.ext@huawei.com/ Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

The bug is triggered when run WARN_ON_ONCE(is_migration_disabled(p)). [ 3298.725394] WARNING: CPU: 73 PID: 0 at kernel/sched/core.c:3147 set_task_cpu+0x18a/0x18e [ 3298.733591] Modules linked in: nf_conntrack_netlink xt_addrtype xt_statistic xt_nat xt_MASQUERADE nft_chain_nat nf_nat xt_mark xt_conntrack xt_comment nft_compat tls nf_tables nfnetlink overlay rfkill qrtr sunrpc ofpart ipmi_si vfat sophgo_spifmc ipmi_devintf spi_nor fat ipmi_msghandler mtd uio_pdrv_genirq uio loop zram ast drm_vram_helper drm_ttm_helper spi_dw_mmio ixgbe spi_dw gpio_dwapb r8169 ttm mdio scsi_dh_rdac scsi_dh_emc scsi_dh_alua ip6_tables ip_tables dm_multipath ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 br_netfilter bridge stp llc [ 3298.785070] CPU: 73 PID: 0 Comm: swapper/73 Not tainted 6.1.31 deepin-community#1 [ 3298.791220] Hardware name: Sophgo Mango (DT) [ 3298.795504] epc : set_task_cpu+0x18a/0x18e [ 3298.799649] ra : load_balance+0x51c/0xb5c [ 3298.803766] epc : ffffffff8004cef6 ra : ffffffff8005dae0 sp : ffffffc80a60bab0 [ 3298.810995] gp : ffffffff81e75e48 tp : ffffffe7feaf1f40 t0 : ffffffc80a60bad0 [ 3298.818216] t1 : 0000000002e2c8d6 t2 : 0000000008016002 s0 : ffffffc80a60baf0 [ 3298.825436] s1 : fffffff00038ddc0 a0 : fffffff00038ddc0 a1 : 000000000000002d [ 3298.832659] a2 : fffffffffe45afe4 a3 : 0000000000000000 a4 : ffffffff81e9c098 [ 3298.839878] a5 : 0000000000000001 a6 : 0000000000000001 a7 : ffffffffffffffff [ 3298.847099] s2 : fffffff00038dea8 s3 : 000000000000002d s4 : 000000000000002d [ 3298.854320] s5 : fffffff65f4fe800 s6 : ffffffff81efb588 s7 : 0000000000000001 [ 3298.861539] s8 : 0000000000000002 s9 : ffffffff81e75d78 s10: ffffffc80a60bbc0 [ 3298.868757] s11: fffffff65f4fe800 t3 : 0000000002845dfc t4 : 00000000000065f9 [ 3298.875983] t5 : 0000000000013dc2 t6 : 000000000000032e [ 3298.881294] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 [ 3298.889211] [<ffffffff8004cef6>] set_task_cpu+0x18a/0x18e [ 3298.894621] [<ffffffff8005dae0>] load_balance+0x51c/0xb5c [ 3298.900026] [<ffffffff8005eb52>] rebalance_domains+0x1f0/0x382 [ 3298.905862] [<ffffffff8005f094>] run_rebalance_domains+0x6a/0x8a [ 3298.911869] [<ffffffff80c6d04c>] __do_softirq+0x18c/0x336 [ 3298.917280] [<ffffffff80020990>] __irq_exit_rcu+0x116/0x148 [ 3298.922866] [<ffffffff80020b22>] irq_exit+0x18/0x28 [ 3298.927745] [<ffffffff80c62c96>] generic_handle_arch_irq+0x64/0x74 [ 3298.933929] [<ffffffff80003dbc>] ret_from_exception+0x0/0x16 [ 3298.939595] [<ffffffff80c62f52>] ct_idle_enter+0x12/0x1a [ 3298.944912] ---[ end trace 0000000000000000 ]--- Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

These are loop counters which is inherently unsigned. Therefore make them unsigned. Moreover it also fixes alloc-size-larger-than error with gcc-13, where malloc can be called with (-1) due to tmp_len being an int type. Fixes | cpumap.c:366:20: error: argument 1 range [18446744065119617024, 18446744073709551612] exceeds maximum object size 9223372036854775807 [-Werror=alloc-size-larger-than=] | 366 | tmp_cpus = malloc(tmp_len * sizeof(struct perf_cpu)); | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Upstream-Status: Submitted [https://lore.kernel.org/linux-perf-users/20230123211310.127532-1-raj.khem@gmail.com/T/#u]

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

dirvers:pci:remove the err log of parsing pci Signed-off-by: fengchun.li <fengchun.li@sophgo.com>

Modified the gpio clock-names in GPIO nodes so mango dts could adapt to Designware gpio controller driver, then gpio bus clock and gpio debounce clock would be enabled. I also force enable the gpio interrupt clock in sophgo clock system so that the gpio interrupt trigger could take effect. Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>

Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>

Basic functionalities have been tested to work fine on pioneer board.

Signed-off-by: lin peng <peng.lin@sophgo.com>

deepin-ci-robot · 2024-09-03T13:19:40Z

deepin pr auto review

Fix build error in RPi 3

Pipermail-Archive-2018-08.txt:

From: Chao.Wei@bitmain.com
Subject: [PATCH] Fix build error in RPi 3

From: Chao.Wei@bitmain.com
Subject: [PATCH] Fix build error in RPi 3

From: Chao.Wei@bitmain.com
Subject: [PATCH] Fix build error in RPi 3

opsiff · 2024-09-03T14:52:26Z

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -1109,6 +1109,8 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 u16 cmd;
 int r;

+ return 0;


这里应该用架构宏隔离吧

opsiff

这个提交ttm: disallow cached mapping 是解决什么问题的？

RevySR · 2024-09-03T15:08:04Z

这个提交ttm: disallow cached mapping 是解决什么问题的？

RISCV SG2042没有PCIE缓存一致性可能需要一个选项

opsiff · 2024-09-03T15:16:55Z

drivers/pci/pcie/portdrv.c

@@ -598,7 +598,7 @@ void pcie_port_service_unregister(struct pcie_port_service_driver *drv)
 }

 /* If this switch is set, PCIe port native services should not be enabled. */
-bool pcie_ports_disabled;
+bool pcie_ports_disabled = true;


这个也需要隔离，不对其他场景生效

Avenger-285714 · 2024-09-04T10:28:28Z

该提交会导致其它架构编译失败，我先加上WIP标签，在问题解决后才可合并

riscv: Add sophgo sg2042 soc support

9b65e1f

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

deepin-ci-robot requested review from hello666888999 and Ink-Paper September 3, 2024 13:17

xingxg2022 and others added 26 commits September 3, 2024 21:18

riscv: errata: Replace thead cache clean with flush

7b48c3d

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

riscv: errata: thead: Make cache clean to flush

b62c4ef

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

riscv: add ioremap_wc for gpu

28e0bb3

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

riscv: spinlock: Fix deadlock issue

a22e0ed

Fix T-Head C9xx store merge buffer delay problem Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>

driver: clk: Add sophgo sg2042 soc support

8638ab1

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

driver: pinctrl: Add sophgo sg2042 soc support

d2cfc74

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

driver: reset: Add sophgo sg2042 soc support

de34681

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

driver: mmc: Add sophgo sg2042 soc support

dfc7cc7

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

driver: net: Add sophgo sg2042 soc support

904c7b1

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

driver: pcie: Add sophgo sg2042 soc support

e3005ee

Signed-off-by: fengchun.li <fengchun.li@sophgo.com>

drivers: pcie: sophgo: Create msi-x whitelist,turn on msi-x for top intr

5bbc425

Turn on msi-x for top intr. Create msi-x whitelist, Limited the number of msi-x interrupts for inter x520 and wangxun NIC. Signed-off-by: chengjun.li <chengjun.li@sophgo.com>

driver: soc: Add sophgo sg2042 soc support

12f1a8f

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

ttm: disallow cached mapping

fbc46f7

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

amdgpu: disable rebar

da1043d

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

radeon hack: force 64-bit msi to fit top intc

b79fed4

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

nvidia hda: force msi

582c866

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

mango pci hack:broadcast when no MSI source known

73cdd0e

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

xingxg2022 and others added 13 commits September 3, 2024 21:18

riscv: kexec: Add image loader for kexec file

c803dae

riscv/kexec: handle R_RISCV_ADD16 and R_RISCV_SUB16 relocation types

bcc9729

refs: https://lore.kernel.org/lkml/f75c763d86529a47eb23d46c5ef9bcbaaf118200.1690274483.git.petr.tesarik.ext@huawei.com/ Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

riscv: kernel: Optimize apply_relocate_add()

210058f

riscv: configs: Add sophgo sg2042 soc defconfig

a87cd4f

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

drivers:pci:remove the err log of parsing pci

b342de0

dirvers:pci:remove the err log of parsing pci Signed-off-by: fengchun.li <fengchun.li@sophgo.com>

dts:sophgo:add i2c-rtc ds1307 device node for single chip

49e3043

Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>

dts:sophgo:x4evb:Apply top interrupt instead of msi on x16 slot

564e66d

Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>

riscv:dts:capricorn:add i2c-rtc device

529aa9c

Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>

pcie: whitelist and support mellanox connectx-2

c0fe527

Basic functionalities have been tested to work fine on pioneer board.

add null event check logic in riscv_pmu_sbi.c

2722614

Signed-off-by: lin peng <peng.lin@sophgo.com>

RevySR force-pushed the deepin/linux-6.6.y/sg2042 branch from 4a8c49a to 2722614 Compare September 3, 2024 13:19

opsiff reviewed Sep 3, 2024

View reviewed changes

Avenger-285714 changed the title ~~[RISCV][SG2042] feat: add sg2042 support~~ [WIP] [RISCV][SG2042] feat: add sg2042 support Sep 4, 2024

deepin-ci-robot added the do-not-merge/work-in-progress label Sep 4, 2024

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[WIP] [RISCV][SG2042] feat: add sg2042 support #399

[WIP] [RISCV][SG2042] feat: add sg2042 support #399

RevySR commented Sep 3, 2024

deepin-ci-robot commented Sep 3, 2024

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opsiff Sep 3, 2024

Avenger-285714 commented Sep 4, 2024

[WIP] [RISCV][SG2042] feat: add sg2042 support #399

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[WIP] [RISCV][SG2042] feat: add sg2042 support #399

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deepin pr auto review

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