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[WIP] [RISCV][SG2042] feat: add sg2042 support #399

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[WIP] [RISCV][SG2042] feat: add sg2042 support #399

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Commits on Sep 3, 2024

  1. riscv: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  2. riscv: errata: Replace thead cache clean with flush 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  3. riscv: errata: cmo: add CMO macro variant with both VA and PA 

    The standardized Zicbom extension supports only VA, however there's some
vendor extensions (e.g. XtheadCmo) that can handle cache management
operations on PA directly, bypassing the TLB lookup.

Add a CMO alternatives macro variant that come with both VA and PA
supplied, and the code can be patched to use either the VA or the PA at
runtime. In this case the codepath is now patched to use VA for Zicbom
and PA for XtheadCmo.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Guo Ren <guoren@kernel.org>
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  4. riscv: use VA+PA variant of CMO macros for DMA synchorization 

    DMA synchorization is done on PA and the VA is calculated from the PA.

Use the alternative macro variant that takes both VA and PA as
parameters, thus in case the ISA extension used support PA directly, the
overhead for re-converting VA to PA can be omitted.

Suggested-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Guo Ren <guoren@kernel.org>
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  5. riscv: use VA+PA variant of CMO macros for DMA page preparation 

    When doing DMA page preparation, both the VA and the PA are easily
accessible from struct page.

Use the alternative macro variant that takes both VA and PA as
parameters, thus in case the ISA extension used support PA directly, the
overhead for re-converting VA to PA can be omitted.

Suggested-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  6. riscv: errata: thead: Make cache clean to flush 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  7. riscv: changing T-Head PBMT attributes 

    Originall the T-Head PBMT implementation in the kernel is intended for
D1, thus the Sharable bit is not set. In addition, the Bufferable bit
is not set for writecombine situation.

Set these bits in the T-Head PBMT attributes definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  8. riscv: add ioremap_wc for gpu 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  9. riscv: add smp_cond_load_acquire() 

    Fix qspinlock issue that loops to call cpu_relax and not exit.
The call trace is:
queued_spin_lock_slowpath->arch_mcs_spin_lock_contended
->smp_cond_load_acquire.

RISCV has not defined smp_cond_load_acquire, so it uses generic
funtion that defined in include/asm-generic/barrier.h.
The generic smp_cond_load_acquire calls smp_cond_load_relaxed that
loops to call READ_ONCE and cpu_relax.
The READ_ONCE need barrier after it to get the new value.
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  10. riscv: spinlock: Fix deadlock issue 

    Fix T-Head C9xx store merge buffer delay problem

Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
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  11. driver: clk: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  12. driver: pinctrl: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  13. driver: reset: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  14. driver: mmc: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  15. driver: mtd: Add sophgo sg2042 soc support 

    Sophgo SPI Flash Master Controller (SPIFMC) is a master controller to
control serial SPI Flash. Enable CONFIG_SPI_SOPHGO_SPIFMC if you have a
device with a SPIFMC controller and want to access the Flash as a mtd
device.

There is GD25LB512ME Serial Flash on SG2042 EVB, controlled by
SPIFMC.

Signed-off-by: jingyu.li01 <jingyu.li01@sophgo.com>
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  16. driver: net: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  17. driver: pcie: Add sophgo sg2042 soc support 

    Signed-off-by: fengchun.li <fengchun.li@sophgo.com>
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  18. drivers: pcie: sophgo: Create msi-x whitelist,turn on msi-x for top intr 

    Turn on msi-x for top intr. Create msi-x whitelist,
Limited the number of msi-x interrupts for inter x520 and wangxun NIC.

Signed-off-by: chengjun.li <chengjun.li@sophgo.com>
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  19. driver: soc: Add sophgo sg2042 soc support 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
    @xingxg2022 @RevySR
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  20. ttm: disallow cached mapping 

    Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  21. amdgpu: disable rebar 

    Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  22. radeon hack: force 64-bit msi to fit top intc 

    Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  23. nvidia hda: force msi 

    Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  24. mango pci hack:broadcast when no MSI source known 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  25. riscv: Add support for kernel-mode FPU 

    This is needed to support recent hardware in the amdgpu DRM driver. The
FPU code in that driver is not performance-critical, so only provide the
minimal support.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  26. riscv: Factor out riscv-march-y to a separate Makefile 

    Since it is not possible to incrementally add/remove extensions from the
compiler's ISA string by appending arguments, any code that wants to
modify the ISA string must recreate the whole thing. To support this,
factor out the logic for generating the -march argument so it can be
reused where needed.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  27. drm/amd/display: Support DRM_AMD_DC_FP on RISC-V 

    RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other
architectures. Enabling hardware FP requires overriding the ISA string
for the relevant compilation units.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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  28. riscv: kexec: Add image loader for kexec file

    @xingxg2022 @RevySR
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  29. riscv/kexec: handle R_RISCV_ADD16 and R_RISCV_SUB16 relocation types 

    refs: https://lore.kernel.org/lkml/f75c763d86529a47eb23d46c5ef9bcbaaf118200.1690274483.git.petr.tesarik.ext@huawei.com/

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  30. riscv: kernel: Optimize apply_relocate_add()

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  31. kernel: schedule: Fix set_task_cpu() bug 

    The bug is triggered when run WARN_ON_ONCE(is_migration_disabled(p)).

[ 3298.725394] WARNING: CPU: 73 PID: 0 at kernel/sched/core.c:3147 set_task_cpu+0x18a/0x18e
[ 3298.733591] Modules linked in: nf_conntrack_netlink xt_addrtype xt_statistic xt_nat xt_MASQUERADE nft_chain_nat nf_nat xt_mark xt_conntrack xt_comment nft_compat tls nf_tables nfnetlink overlay rfkill qrtr sunrpc ofpart ipmi_si vfat sophgo_spifmc ipmi_devintf spi_nor fat ipmi_msghandler mtd uio_pdrv_genirq uio loop zram ast drm_vram_helper drm_ttm_helper spi_dw_mmio ixgbe spi_dw gpio_dwapb r8169 ttm mdio scsi_dh_rdac scsi_dh_emc scsi_dh_alua ip6_tables ip_tables dm_multipath ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 br_netfilter bridge stp llc
[ 3298.785070] CPU: 73 PID: 0 Comm: swapper/73 Not tainted 6.1.31 deepin-community#1
[ 3298.791220] Hardware name: Sophgo Mango (DT)
[ 3298.795504] epc : set_task_cpu+0x18a/0x18e
[ 3298.799649]  ra : load_balance+0x51c/0xb5c
[ 3298.803766] epc : ffffffff8004cef6 ra : ffffffff8005dae0 sp : ffffffc80a60bab0
[ 3298.810995]  gp : ffffffff81e75e48 tp : ffffffe7feaf1f40 t0 : ffffffc80a60bad0
[ 3298.818216]  t1 : 0000000002e2c8d6 t2 : 0000000008016002 s0 : ffffffc80a60baf0
[ 3298.825436]  s1 : fffffff00038ddc0 a0 : fffffff00038ddc0 a1 : 000000000000002d
[ 3298.832659]  a2 : fffffffffe45afe4 a3 : 0000000000000000 a4 : ffffffff81e9c098
[ 3298.839878]  a5 : 0000000000000001 a6 : 0000000000000001 a7 : ffffffffffffffff
[ 3298.847099]  s2 : fffffff00038dea8 s3 : 000000000000002d s4 : 000000000000002d
[ 3298.854320]  s5 : fffffff65f4fe800 s6 : ffffffff81efb588 s7 : 0000000000000001
[ 3298.861539]  s8 : 0000000000000002 s9 : ffffffff81e75d78 s10: ffffffc80a60bbc0
[ 3298.868757]  s11: fffffff65f4fe800 t3 : 0000000002845dfc t4 : 00000000000065f9
[ 3298.875983]  t5 : 0000000000013dc2 t6 : 000000000000032e
[ 3298.881294] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
[ 3298.889211] [<ffffffff8004cef6>] set_task_cpu+0x18a/0x18e
[ 3298.894621] [<ffffffff8005dae0>] load_balance+0x51c/0xb5c
[ 3298.900026] [<ffffffff8005eb52>] rebalance_domains+0x1f0/0x382
[ 3298.905862] [<ffffffff8005f094>] run_rebalance_domains+0x6a/0x8a
[ 3298.911869] [<ffffffff80c6d04c>] __do_softirq+0x18c/0x336
[ 3298.917280] [<ffffffff80020990>] __irq_exit_rcu+0x116/0x148
[ 3298.922866] [<ffffffff80020b22>] irq_exit+0x18/0x28
[ 3298.927745] [<ffffffff80c62c96>] generic_handle_arch_irq+0x64/0x74
[ 3298.933929] [<ffffffff80003dbc>] ret_from_exception+0x0/0x16
[ 3298.939595] [<ffffffff80c62f52>] ct_idle_enter+0x12/0x1a
[ 3298.944912] ---[ end trace 0000000000000000 ]---

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  32. perf cpumap: Make counter as unsigned ints 

    These are loop counters which is inherently unsigned. Therefore make
them unsigned. Moreover it also fixes alloc-size-larger-than
error with gcc-13, where malloc can be called with (-1) due to tmp_len
being an int type.

Fixes
| cpumap.c:366:20: error: argument 1 range [18446744065119617024, 18446744073709551612] exceeds maximum object size 9223372036854775807 [-Werror=alloc-size-larger-than=]
|   366 |         tmp_cpus = malloc(tmp_len * sizeof(struct perf_cpu));
|       |                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>

Upstream-Status: Submitted [https://lore.kernel.org/linux-perf-users/20230123211310.127532-1-raj.khem@gmail.com/T/#u]
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  33. riscv: configs: Add sophgo sg2042 soc defconfig 

    Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
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  34. drivers:pci:remove the err log of parsing pci 

    dirvers:pci:remove the err log of parsing pci

Signed-off-by: fengchun.li <fengchun.li@sophgo.com>
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  35. riscv:dts:modify dw gpio clock name 

    Modified the gpio clock-names in GPIO nodes so mango dts could
adapt to Designware gpio controller driver, then gpio bus clock
and gpio debounce clock would be enabled.
I also force enable the gpio interrupt clock in sophgo clock
system so that the gpio interrupt trigger could take effect.

Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>
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  36. dts:sophgo:add i2c-rtc ds1307 device node for single chip 

    Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>
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  37. dts:sophgo:x4evb:Apply top interrupt instead of msi on x16 slot 

    Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>
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  38. riscv:dts:capricorn:add i2c-rtc device 

    Signed-off-by: chunzhi.lin <chunzhi.lin@sophgo.com>
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  39. pcie: whitelist and support mellanox connectx-2 

    Basic functionalities have been tested to work fine on pioneer board.
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  40. add null event check logic in riscv_pmu_sbi.c 

    Signed-off-by: lin peng <peng.lin@sophgo.com>
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