Add Lighter to Yosys.Synthesis

nix/yosys-lighter.nix

@@ -44,6 +44,22 @@ with pkgs; clangStdenv.mkDerivation rec {
   installPhase = ''
   mkdir -p $out/share/yosys/plugins
   cp lighter.so $out/share/yosys/plugins
+
+  mkdir -p $out/bin
+  cat << HD > $out/bin/lighter_files
+  #!/bin/sh
+  if [ "\$1" = "" ]; then
+    echo "Usage: \$0 <scl>" >> /dev/stderr
+    exit 1
+  fi
+  find $out/share/lighter_maps/\$1 -type f
+  HD
+  chmod +x $out/bin/lighter_files
+
+  mkdir -p $out/share/lighter_maps
+  cp -r platform/* $out/share/lighter_maps
+  rm -rf $out/share/lighter_maps/**/*.lib
+  rm -rf $out/share/lighter_maps/**/*_blackbox.v
   '';
 
   computed_PATH = lib.makeBinPath propagatedBuildInputs;

openlane/config/removals.py

@@ -31,4 +31,5 @@
     "PL_ESTIMATE_PARASITICS": "Parasitics are always estimated whenever possible.",
     "GRT_ESTIMATE_PARASITICS": "Parasitics are always estimated whenever possible.",
     "FP_PDN_AUTO_ADJUST": "Too situational. It's always best to be more explicit.",
+    "SYNTH_READ_BLACKBOX_LIB": "Always on.",
 }

openlane/scripts/openroad/sta/corner.tcl

@@ -121,6 +121,16 @@ puts " report_power"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
 report_power -corner [$corner name]
+
+set power_result [sta::design_power $corner]
+set totals       [lrange $power_result  0  3]
+lassign $totals design_internal design_switching design_leakage design_total
+
+write_metric_num "power__internal__total" $design_internal
+write_metric_num "power__switching__total" $design_switching
+write_metric_num "power__leakage__total" $design_leakage
+write_metric_num "power__total" $design_total
+
 puts ""
 puts "%OL_END_REPORT"
 

openlane/scripts/yosys/common.tcl

@@ -26,11 +26,9 @@ proc read_deps {{power_defines "off"}} {
         }
     }
 
-    if { $::env(SYNTH_READ_BLACKBOX_LIB) } {
-        foreach lib $::env(FULL_LIBS) {
-            log "Reading SCL library '$lib' as a blackbox…"
-            read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
-        }
+    foreach lib $::env(FULL_LIBS) {
+        log "Reading SCL library '$lib' as a blackbox…"
+        read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
     }
 
     if { [info exists ::env(MACRO_LIBS) ] } {

openlane/scripts/yosys/synthesize.tcl

@@ -259,6 +259,12 @@ if { $adder_type == "RCA"} {
 }
 
 hierarchy -check -auto-top
+
+if { [info exists ::env(_lighter_dff_map)] } {
+    puts "Using Lighter with map '$::env(_lighter_dff_map)'…"
+    reg_clock_gating -map $::env(_lighter_dff_map)
+}
+
 proc_clean
 proc_rmdead
 proc_prune

openlane/steps/step.py

@@ -37,7 +37,7 @@
     ClassVar,
     Type,
 )
-from rich.console import escape
+from rich.markup import escape
 
 from ..config import (
     Config,

openlane/steps/yosys.py

@@ -26,7 +26,7 @@
 
 from ..config import Variable, Config
 from ..state import State, DesignFormat
-from ..logging import debug, verbose, info
+from ..logging import debug, verbose, info, warn
 from ..common import Path, get_script_dir, Toolbox, TclUtils
 
 starts_with_whitespace = re.compile(r"^\s+.+$")
@@ -78,12 +78,6 @@ class YosysStep(TclStep):
             Optional[List[str]],
             "Specifies the Verilog `include` directories.",
         ),
-        Variable(
-            "SYNTH_READ_BLACKBOX_LIB",
-            bool,
-            "Additionally read the liberty file(s) as a blackbox. This will allow RTL designs to incorporate explicitly declared standard cells that will not be tech-mapped or reinterpreted.",
-            default=False,
-        ),
         Variable(
             "SYNTH_LATCH_MAP",
             Optional[Path],
@@ -130,6 +124,17 @@ class YosysStep(TclStep):
             "A path to a file containing the mux4 mapping for Yosys.",
             pdk=True,
         ),
+        Variable(
+            "USE_LIGHTER",
+            bool,
+            "Activates Lighter, an experimental module that attempts to optimize clock-gated flip-flops.",
+            default=False,
+        ),
+        Variable(
+            "LIGHTER_DFF_MAP",
+            Optional[Path],
+            "An override to the custom DFF map file provided for the given SCL by Lighter.",
+        ),
     ]
 
     def get_command(self) -> List[str]:
@@ -142,6 +147,26 @@ def get_script_path(self) -> str:
 
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         kwargs, env = self.extract_env(kwargs)
+
+        if self.config["USE_LIGHTER"]:
+            lighter_dff_map = self.config["LIGHTER_DFF_MAP"]
+            if lighter_dff_map is None:
+                scl = self.config["STD_CELL_LIBRARY"]
+                try:
+                    raw = subprocess.check_output(
+                        ["lighter_files", scl], encoding="utf8"
+                    )
+                    files = raw.strip().splitlines()
+                    lighter_dff_map = Path(files[0])
+                except FileNotFoundError:
+                    warn(
+                        f"Lighter not found or not set up with OpenLane: If you're using a manual Lighter install, try setting the DFF map explicitly."
+                    )
+                except subprocess.CalledProcessError:
+                    warn(f"{scl} not supported by Lighter.")
+
+            env["_lighter_dff_map"] = lighter_dff_map
+
         lib_list = [
             str(e) for e in self.toolbox.filter_views(self.config, self.config["LIB"])
         ]
@@ -368,12 +393,9 @@ def _generate_read_deps(
             flag = TclUtils.escape(f"-D{define}")
             commands += f"verilog_defines {flag}"
 
-    if config["SYNTH_READ_BLACKBOX_LIB"]:
-        for lib in toolbox.filter_views(config, config["LIB"]):
-            lib_str = TclUtils.escape(str(lib))
-            commands += (
-                f"read_liberty -lib -ignore_miss_dir -setattr blackbox {lib_str}\n"
-            )
+    for lib in toolbox.filter_views(config, config["LIB"]):
+        lib_str = TclUtils.escape(str(lib))
+        commands += f"read_liberty -lib -ignore_miss_dir -setattr blackbox {lib_str}\n"
 
     for lib in toolbox.get_macro_views(config, DesignFormat.LIB):
         lib_str = TclUtils.escape(str(lib))