update glossary; remove mathjax path

docs/source/conf.py

@@ -147,9 +147,6 @@
 # GraphViz
 graphviz_output_format = "svg"
 
-# MathJax
-mathjax_path = "https://cdnjs.cloudflare.com/ajax/libs/mathjax/3.2.2/es5/latest.min.js"
-
 # sphinx_copybutton
 copybutton_exclude = ".linenos, .gp"
 

docs/source/getting_started/newcomers/index.md

@@ -251,8 +251,8 @@ Here is a small description of each file inside a `Step` directory.
 - `config.json`: contains `Variables` used by the `Step`
 - `*.log`: one or more log file of the `Step`
 - `*.process_stats.json`: statistics about total elapsed time and resource consumption
-- `state_in.json`: contains a dictionary of design artifacts (TODO:correct word?) (such as `DEF` file)
-  and design `Metrics` available as inputs to a `Step` .
+- `state_in.json`: contains a dictionary of design layout formats (such as `DEF`
+  file) and design `Metrics` available as inputs to a `Step` .
 - `state_out.json`: An updated `state_in.json`. For example, If a step generates
   a new `DEF` file it would be updated otherwise, it is a copy of `state_in.json`.
 - `or_metrics_out.json`: It contains new or updated `Metrics` generated by the
@@ -411,7 +411,7 @@ Common `LVS` errors include but are not limited to:
 
 `Netgen.LVS` is the `Step` ran for `LVS` using a tool called
 {term}`Netgen`. First, the layout is converted to
-{term}`SPICE` netlist. Next
+{term}`SPICE netlist`. Next
 the layout and the schematic are inputted to Netgen, as shown in the diagram
 bellow.
 
@@ -743,7 +743,8 @@ SPM with 5% utilization
 :::{tip}
 You can control the visible layers in KLayout by right clicking in the layers
 area and selecting hide all layers. Then double click on the layers that you want
-to view. In this figure, only met2.pin, met3.pin and pr.prboundary are shown.
+to view. In this figure, only `met2.pin`, `met3.pin` and `prBoundary.boundary`
+are shown.
 :::
 
 As shown above, the are a lot of pins needed by the design and
@@ -766,9 +767,9 @@ can achieve that by using the variable `FP_DEF_TEMPLATE`. `FP_DEF_TEMPLATE` is a
 locations are copied from the template `DEF` file over to our design. In addition,
 the same die area is used as the one in the template `DEF` file.
 
-Save this file (TODO: insert def template link), in your design's directory
-which should be `~/my_designs/spm-user_project_wrapper/`. Then update the design's
-configuration by adding `FP_DEF_TEMPLATE` variable:
+Save this file [template.def](../../../../openlane/examples/spm-user_project_wrapper/template.def),
+in your design's directory which should be `~/my_designs/spm-user_project_wrapper/`.
+Then update the design's configuration by adding `FP_DEF_TEMPLATE` variable:
 
 ```json
 {
@@ -804,7 +805,7 @@ this area.
 ```{figure} ./caravel-pdn-2.png
 :align: center
 
-Top right corner
+Top right corner of macro integrated inside Caravel
 ```
 
 As highlighted there are power rings surrounding our wrapper. connectivity
@@ -833,15 +834,13 @@ Append the following variables to your configuration:
 ```
 
 :::{seealso}
-Visit TODO: Insert PDN config vars link here. For more information about
-each of the above variables
+Visit [`OpenROAD.GeneratePDN`](#step-openroad-generatepdn) for more information
+about each of the above variables
 :::
 
 `Caravel` is a chip with multiple power domains. We need to match these domains
 in our configuration by updating `VDD_NETS` and `GND_NETS` variables:
 
-? Should we mention "power domains here".
-
 ```json
     "VDD_NETS": [
         "vccd1",

docs/source/glossary.md

@@ -13,10 +13,11 @@ timing corner
 Nix
     Nix is a tool that takes a unique approach to package management and system
     configuration. Learn how to make reproducible, declarative and reliable systems.
-    See more [here](https://nixos.org/)
+    For more information visit [https://nixos.org/](https://nixos.org/).
 
 cachix
-    Insert description here
+    Cachix is a service for Nix binary cache hosting.
+    For more information visit [https://docs.cachix.org/](https://docs.cachix.org/).
 
 sky130
     The SkyWater Open Source PDK is a collaboration between Google, Efabless and
@@ -27,14 +28,22 @@ sky130
     SkyWater Technology and made accessible to general industry.
 
 PDK
-    Stands for Process Design Kit
+    Stands for Process Design Kit is a set of files used within the
+    semiconductor industry to model a fabrication process for the design
+    tools used to design an integrated circuit.
 
 RTL
-    Stands for Register transfer level
+    Stands for Register Transfer Level.
+    Register-transfer-level abstraction is used in hardware description languages
+    (HDLs) like Verilog and VHDL to create high-level representations of a
+    circuit, from which lower-level representations and ultimately actual wiring
+    can be derived. Design at the RTL level is typical practice in modern digital
+    design.
 
 Variable
     An OpenLane configuration variable. It used to control steps and flows.
-    <insert ref here>
+    For more information visit {doc}`./reference/flows` and
+    {doc}`./reference/step_config_vars`.
 
 GDSII
     Stands for Graphic design system. It is a binary stream format which is the
@@ -48,22 +57,28 @@ GDSII
 
 KLayout
     A free and open-source layout viewer and editor. For more information visit
-    https://www.klayout.de/
+    [https://www.klayout.de/](https://www.klayout.de/).
 
 OpenROAD
     An open-source tool chain for digital SoC layout generation, focusing on the
     RTL-to-GDSII phase of system-on-chip design. It is used for floorplanning,
     design optimizations, placement, CTS(Clock Tree Synthesis) and routing inside
-    OpenLane. For more information visit https://openroad.readthedocs.io/en/latest/
+    OpenLane. For more information visit
+    [https://openroad.readthedocs.io/en/latest/](https://openroad.readthedocs.io/en/latest/).
 
 Flow
-    Insert description here
+    Flows encapsulates a subroutine that runs multiple steps: either
+    synchronously, asynchronously, serially or in any manner.
+    For more information visit {py:class}`openlane.flows.Flow`.
 
 Step
-    Insert description here
+    Steps encapsulate a subroutine that acts upon certain classes of formats in
+    an input state and returns a new output state with updated design format
+    paths and/or metrics.
+    For more information visit {py:class}`openlane.steps.Step`.
 
 Metrics
-    Insert description here
+    TODO: Insert description here
 
 DEF
     Stands for Design Exchange Format. A DEF file contains representation of the
@@ -85,12 +100,18 @@ Verilog
     Verilog is a hardware description language (HDL) used to model electronic
     systems. It is most commonly used in the design and verification of digital
     circuits at the register-transfer level (RTL) of abstraction.
-    TODO (from wiki.. is that bad ?)
 
 Netgen
     A free and open-source tool for running Layout Versus Schematic (LVS).
-
-SPICE
-    Insert description here
+    For more information visit
+    [http://opencircuitdesign.com/netgen/](http://opencircuitdesign.com/netgen/).
+
+SPICE netlist
+    SPICE stands for Simulation Program with Integrated Circuit Emphasis.
+    A SPICE netlist is a textual representation of a design. Generally,
+    it has more information than a Verilog netlist, especially regarding
+    parasitics. It is typically used to perform SPICE simulations to verify the
+    functionality of the design.
+    TODO: check
 
 ```