feat: expose some CTS options

Changelog.md

@@ -14,6 +14,15 @@
 ## Documentation
 -->
 
+# Dev
+
+## Steps
+
+* `OpenROAD.CTS`
+  * Added flags `CTS_OBSTRUCTION_AWARE` and `CTS_BALANCE_LEVELS`
+  * Added `CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT`
+  * Added `CTS_DELAY_BUFFER_DERATE_PCT`
+
 # 2.2.9
 
 ## Steps

openlane/scripts/openroad/cts.tcl

@@ -50,11 +50,23 @@ lappend arg_list -sink_clustering_enable
 if { $::env(CTS_DISTANCE_BETWEEN_BUFFERS) != 0 } {
     lappend arg_list -distance_between_buffers $::env(CTS_DISTANCE_BETWEEN_BUFFERS)
 }
-
 if { $::env(CTS_DISABLE_POST_PROCESSING) } {
     lappend arg_list -post_cts_disable
 }
+if { [info exists ::env(CTS_OBSTRUCTION_AWARE)] && $::env(CTS_OBSTRUCTION_AWARE) } {
+    lappend arg_list -obstruction_aware
+}
+if { [info exists ::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT)] } {
+    lappend arg_list -sink_buffer_max_cap_derate [expr $::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT) / 100.0]
+}
+if { [info exists ::env(CTS_DELAY_BUFFER_DERATE_PCT)] } {
+    lappend arg_list -delay_buffer_derate [expr $::env(CTS_DELAY_BUFFER_DERATE_PCT) / 100]
+}
+if { [info exists ::env(CTS_BALANCE_LEVELS)] && $::env(CTS_BALANCE_LEVELS) } {
+    lappend arg_list -balance_levels
+}
 
+puts "clock_tree_synthesis {*}$arg_list"
 clock_tree_synthesis {*}$arg_list
 
 set_propagated_clock [all_clocks]

openlane/steps/openroad.py

@@ -2012,6 +2012,32 @@ class CTS(ResizerStep):
         OpenROADStep.config_vars
         + dpl_variables
         + [
+            # sink_buffer_max_cap_derate
+            Variable(
+                "CTS_BALANCE_LEVELS",
+                Optional[bool],
+                "Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).",
+            ),
+            Variable(
+                "CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT",
+                Optional[Decimal],
+                "Controls automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value."
+                + "The value of 100 means no derating of max cap limit",
+                units="%",
+            ),
+            Variable(
+                "CTS_DELAY_BUFFER_DERATE_PCT",
+                Optional[Decimal],
+                "This option balances latencies between macro cells and registers by inserting delay buffers"
+                + "The value of 100 means all needed delay buffers are inserted",
+                units="%",
+            ),
+            Variable(
+                "CTS_OBSTRUCTION_AWARE",
+                Optional[bool],
+                "Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. "
+                + "This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.",
+            ),
             Variable(
                 "CTS_SINK_CLUSTERING_SIZE",
                 int,