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[SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency #6693

[SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency

[SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency #6693

Triggered via pull request July 16, 2024 22:01
Status Success
Total duration 3h 4m 20s
Artifacts 1

sycl-windows-precommit.yml

on: pull_request
detect_changes  /  Decide which tests could be affected by the changes
6s
detect_changes / Decide which tests could be affected by the changes
e2e  /  Intel GEN12 Graphics with Level Zero
38m 56s
e2e / Intel GEN12 Graphics with Level Zero
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2 warnings
build / Build + LIT
The following actions uses Node.js version which is deprecated and will be forced to run on node20: ./src/devops/actions/cleanup. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
e2e / Intel GEN12 Graphics with Level Zero
The following actions uses Node.js version which is deprecated and will be forced to run on node20: ./llvm/devops/actions/cleanup. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/

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sycl_windows_default Expired
520 MB