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[SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency #14566

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merged 11 commits into from
Jul 17, 2024

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@smanna12 smanna12 commented Jul 13, 2024

This commit refactors the CheckValidFPGAMemoryAttributesVar function in SemaDeclAttr.cpp to improve the clarity and efficiency of the validation logic for 11 FPGA memory attributes on variables. The updated implementation streamlines the condition checks, making the code easier to read and understand.

Key changes include:
- Simplifying the conditional logic to reduce complexity.
- Using direct return statements for immediate feedback on validation status.
- Enhancing readability by clearly separating checks for different variable types and attributes.

This refactor ensures that the function more clearly expresses its intent, making the codebase more accessible for future development and optimizations.

No functional changes are intended with this refactor; it aims solely at improving code quality and readability.

Signed-off-by: Soumi Manna soumi.manna@intel.com

…LIntelRegister, SYCLIntelMemory)

This patch uses MutualExclusions tablegen support to allow us to remove a
custom diagnostic checking codes with FPGA attributes:
[[intel:fpga_register]] and [[intel::fpga_memory]].

No test is added as we alreday have an existing LIT test (SemaSYCL/local.cpp) that shows the behavior.
…ency

This commit refactors the CheckValidFPGAMemoryAttributesVar function in SemaDeclAttr.cpp to improve the clarity and efficiency of the validation logic for FPGA memory attributes on variables. The updated implementation streamlines the condition checks, making the code easier to read and understand.

Key changes include:
- Simplifying the conditional logic to reduce complexity.
- Using direct return statements for immediate feedback on validation status.
- Enhancing readability by clearly separating checks for different variable types and attributes.

This refactor ensures that the function more clearly expresses its intent, making the codebase more accessible for future development and optimizations.

No functional changes are intended with this refactor; it aims solely at improving code quality and readability.

Signed-off-by: Soumi Manna <soumi.manna@intel.com>
@smanna12 smanna12 changed the title Refactor fpga mem attr [SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency Jul 13, 2024
@smanna12 smanna12 marked this pull request as ready for review July 16, 2024 22:08
@smanna12 smanna12 requested a review from a team as a code owner July 16, 2024 22:08
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smanna12 commented Jul 17, 2024

The failure is unrelated to my patch:
https://github.com/intel/llvm/actions/runs/9964711068/job/27540867428?pr=14566

Failed Tests (1):
SYCL :: abi/sycl_classes_abi_neutral_test.cpp

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Thank you @elizabethandrews for reviews!

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@intel/llvm-gatekeepers, This PR is ready to merge. Thank you

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sarnex commented Jul 17, 2024

  SYCL :: abi/sycl_classes_abi_neutral_test.cpp

not related and already fixed in other commit

@sarnex sarnex merged commit 3ae9361 into intel:sycl Jul 17, 2024
13 of 14 checks passed
@smanna12 smanna12 deleted the RefactorFPGAMemAttr branch July 17, 2024 15:25
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3 participants