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[SYCL] Refactor FPGA Memory Attributes Validation for Clarity and and Efficiency #14566

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merged 11 commits into from
Jul 17, 2024

Commits on Mar 26, 2024

  1. [SYCL][FPGA] Allow tablegen handle mutually exclusive decl attrs (SYC…

    …LIntelRegister, SYCLIntelMemory)
    
    This patch uses MutualExclusions tablegen support to allow us to remove a
    custom diagnostic checking codes with FPGA attributes:
    [[intel:fpga_register]] and [[intel::fpga_memory]].
    
    No test is added as we alreday have an existing LIT test (SemaSYCL/local.cpp) that shows the behavior.
    smanna12 committed Mar 26, 2024
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Commits on Mar 28, 2024

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Commits on Jul 13, 2024

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  2. Refactor FPGA Memory Attributes Validation for Clarity and and Effici…

    …ency
    
    This commit refactors the CheckValidFPGAMemoryAttributesVar function in SemaDeclAttr.cpp to improve the clarity and efficiency of the validation logic for FPGA memory attributes on variables. The updated implementation streamlines the condition checks, making the code easier to read and understand.
    
    Key changes include:
    - Simplifying the conditional logic to reduce complexity.
    - Using direct return statements for immediate feedback on validation status.
    - Enhancing readability by clearly separating checks for different variable types and attributes.
    
    This refactor ensures that the function more clearly expresses its intent, making the codebase more accessible for future development and optimizations.
    
    No functional changes are intended with this refactor; it aims solely at improving code quality and readability.
    
    Signed-off-by: Soumi Manna <soumi.manna@intel.com>
    smanna12 committed Jul 13, 2024
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  3. Fix format

    smanna12 committed Jul 13, 2024
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  4. Update patch

    smanna12 committed Jul 13, 2024
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Commits on Jul 16, 2024

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