[SYCL][COMPAT] NVPTX nd_range_barrier seq_cst memory order

intel · Apr 9, 2024 · 1d8aaa4 · 1d8aaa4
1 parent 1ff4250
commit 1d8aaa4
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Showing 2 changed files with 3 additions and 5 deletions.
diff --git a/sycl/doc/syclcompat/README.md b/sycl/doc/syclcompat/README.md
@@ -1129,8 +1129,8 @@ spec, and so should be used with caution.
 namespace syclcompat {
 namespace experimental {
 
- #if defined(__AMDGPU__) || defined(__NVPTX__)
-// seq_cst currently not working with AMD and Nvidia Backends
+#if defined(__AMDGPU__)
+// seq_cst currently not working for AMD
 constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::acq_rel;
 #else
 constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::seq_cst;

diff --git a/sycl/include/syclcompat/util.hpp b/sycl/include/syclcompat/util.hpp
@@ -281,9 +281,7 @@ inline int get_sycl_language_version() {
 
 namespace experimental {
 
-#if defined(__AMDGPU__) || defined(__NVPTX__)
-// FIXME: https://github.com/intel/llvm/pull/12516 adds seq_cst support for the
-// CUDA backend.
+#if defined(__AMDGPU__)
 constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::acq_rel;
 #else
 constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::seq_cst;