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[Driver][SYCL] Address issue with improper bundler call with -fsycl-link #13002

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Mar 19, 2024
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29 changes: 7 additions & 22 deletions clang/lib/Driver/Driver.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5050,7 +5050,7 @@ class OffloadingActionBuilder final {
for (auto SDA : SYCLDeviceActions)
SYCLLinkBinaryList.push_back(SDA);
if (WrapDeviceOnlyBinary)
return ABRT_Success;
return ABRT_Ignore_Host;
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auto *Link =
C.MakeAction<LinkJobAction>(SYCLLinkBinaryList, types::TY_Image);
SYCLLinkBinary =
Expand Down Expand Up @@ -6749,9 +6749,8 @@ class OffloadingActionBuilder final {
return false;
if (HasFPGATarget && !updateInputForFPGA(A, InputArg, Args))
return false;
// FIXME - unbundling action is being split into two different actions
// when unbundling objects. One action for the host, the other for the
// device.
// FIXME - unbundling action with -fsycl-link is unbunding for both host
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// and device, where only the device is needed.
auto UnbundlingHostAction = C.MakeAction<OffloadUnbundlingJobAction>(
A, (HasSPIRTarget && HostAction->getType() == types::TY_Archive)
? types::TY_Tempfilelist
Expand Down Expand Up @@ -7325,7 +7324,6 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
ExtractAPIJobAction *ExtractAPIAction = nullptr;
ActionList LinkerInputs;
ActionList MergerInputs;
ActionList DeviceAOTLinkerInputs;
ActionList HostActions;
llvm::SmallVector<const Arg *, 6> LinkerInputArgs;
llvm::SmallVector<phases::ID, phases::MaxNumberOfPhases> PL;
Expand Down Expand Up @@ -7362,17 +7360,6 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
if (Phase == phases::Link) {
assert(Phase == PL.back() && "linking must be final compilation step.");

// When performing -fsycl-link the current inputs are not expected to
// be passed to the final host link step. Instead, take these inputs
// and redirect them to the associated wrapping step to create the
// final object.
if (C.getInputArgs().hasArg(options::OPT_fsycl_link_EQ) &&
!Args.hasArg(options::OPT_fintelfpga)) {
DeviceAOTLinkerInputs.push_back(Current);
Current = nullptr;
break;
}

// We don't need to generate additional link commands if emitting AMD
// bitcode or compiling only for the offload device
if (!(C.getInputArgs().hasArg(options::OPT_hip_link) &&
Expand Down Expand Up @@ -7515,11 +7502,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
Arg *FinalPhaseArg;
if (!UseNewOffloadingDriver &&
getFinalPhase(Args, &FinalPhaseArg) == phases::Link) {
if (LinkerInputs.empty() && DeviceAOTLinkerInputs.empty())
OffloadBuilder->appendDeviceLinkActions(Actions);

if (!DeviceAOTLinkerInputs.empty() &&
Args.hasArg(options::OPT_fsycl_link_EQ) &&
if (Args.hasArg(options::OPT_fsycl_link_EQ) &&
!Args.hasArg(options::OPT_fintelfpga)) {
ActionList LAList;
OffloadBuilder->makeHostLinkDeviceOnlyAction(LAList);
Expand All @@ -7528,7 +7511,8 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
LA = OffloadBuilder->processHostLinkAction(LA);
Actions.push_back(LA);
}
}
} else if (LinkerInputs.empty())
OffloadBuilder->appendDeviceLinkActions(Actions);
}

if (!LinkerInputs.empty()) {
Expand Down Expand Up @@ -8999,6 +8983,7 @@ InputInfoList Driver::BuildJobsForActionNoCache(
InputInfo CurI;
bool IsFPGAObjLink =
(JA->getType() == types::TY_Object &&
EffectiveTriple.getSubArch() == llvm::Triple::SPIRSubArch_fpga &&
C.getInputArgs().hasArg(options::OPT_fsycl_link_EQ));
if (C.getDriver().getOffloadStaticLibSeen() &&
(JA->getType() == types::TY_Archive ||
Expand Down
21 changes: 21 additions & 0 deletions clang/test/Driver/sycl-offload.c
Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,27 @@
// CHK-LINK-UB: 10: backend, {9}, assembler, (host-sycl)
// CHK-LINK-UB: 11: assembler, {10}, object, (host-sycl)

/// Check -fsycl-link tool calls
// RUN: %clangxx -### --target=x86_64-unknown-linux-gnu -fsycl -o %t.out \
// RUN: -fsycl-targets=spir64_gen -fsycl-link \
// RUN: -fno-sycl-device-lib=all %t.o 2>&1 \
// RUN: | FileCheck -check-prefixes=CHK-FSYCL-LINK-UB,CHK-FSYCL-LINK-UB-LIN %s
// RUN: %clang_cl -### --target=x86_64-pc-windows-msvc -fsycl -o %t.out \
// RUN: -fsycl-targets=spir64_gen -fsycl-link \
// RUN: -fno-sycl-device-lib=all %t.o 2>&1 \
// RUN: | FileCheck -check-prefixes=CHK-FSYCL-LINK-UB,CHK-FSYCL-LINK-UB-WIN %s
// CHK-FSYCL-LINK-UB: clang-offload-bundler{{.*}} "-type=o" "-targets=host{{.*}},sycl-spir64_gen-unknown-unknown" "-input=[[INPUT:.+\.o]]" "-output={{.*}}" "-output=[[DEVICE_O:.+]]" "-unbundle"
// CHK-FSYCL-LINK-UB: spirv-to-ir-wrapper{{.*}} "[[DEVICE_O]]" "-o" "[[DEVICE_BC:.+\.bc]]"
// CHK-FSYCL-LINK-UB: llvm-link{{.*}} "[[DEVICE_BC]]"
// CHK-FSYCL-LINK-UB: sycl-post-link{{.*}} "-o" "[[POST_LINK_TABLE:.+\.table]]"
// CHK-FSYCL-LINK-UB: file-table-tform{{.*}} "-o" "[[TFORM_TABLE:.+\.txt]]" "[[POST_LINK_TABLE]]"
// CHK-FSYCL-LINK-UB: llvm-spirv{{.*}} "-o" "[[SPIRV:.+\.txt]]"{{.*}} "[[TFORM_TABLE]]"
// CHK-FSYCL-LINK-UB-LIN: ocloc{{.*}} "-output" "[[OCLOC_OUT:.+\.out]]
// CHK-FSYCL-LINK-UB-WIN: ocloc{{.*}} "-output" "[[OCLOC_OUT:.+\.exe]]
// CHK-FSYCL-LINK-UB: file-table-tform{{.*}} "-o" "[[TFORM_TABLE2:.+\.table]]" "[[POST_LINK_TABLE]]" "[[OCLOC_OUT]]"
// CHK-FSYCL-LINK-UB: clang-offload-wrapper{{.*}} "-o" "[[WRAPPER_OUT:.+\.bc]]"{{.*}} "-batch" "[[TFORM_TABLE2]]"
// CHK-FSYCL-LINK-UB: clang{{.*}} "-cc1"{{.*}} "-o" "{{.*}}.out" "-x" "ir" "[[WRAPPER_OUT]]"

/// Check -fsycl-link AOT unbundle
// RUN: %clang -### -ccc-print-phases -target x86_64-unknown-linux-gnu \
// RUN: -fsycl -o %t.out -fsycl-link -fno-sycl-instrument-device-code \
Expand Down
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