Add missing GPIO_SD peripheral for ESP32-H2 and correct base addres…

…s for ESP32-C6 (esp-rs#162)

* Correct base address of `GPIO_SD` peripheral for ESP32-C6

* Add missing `GPIO_SD` peripheral for ESP32-H2

esp32c6/src/lib.rs

@@ -737,7 +737,7 @@ pub struct GPIO_SD {
 unsafe impl Send for GPIO_SD {}
 impl GPIO_SD {
     #[doc = r"Pointer to the register block"]
-    pub const PTR: *const gpio_sd::RegisterBlock = 0x6000_4f00 as *const _;
+    pub const PTR: *const gpio_sd::RegisterBlock = 0x6009_1f00 as *const _;
     #[doc = r"Return the pointer to the register block"]
     #[inline(always)]
     pub const fn ptr() -> *const gpio_sd::RegisterBlock {

esp32c6/svd/patches/esp32c6.yaml

@@ -1,5 +1,8 @@
 _svd: "../esp32c6.base.svd"
 
+_modify:
+  GPIO_SD:
+    baseAddress: 0x60091f00
 
 USB_DEVICE:
   _modify:

esp32h2/src/gpio_sd.rs

@@ -0,0 +1,124 @@
+#[doc = r"Register block"]
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x10 - Duty Cycle Configure Register of SDM%s"]
+    pub sigmadelta: [SIGMADELTA; 4],
+    _reserved1: [u8; 0x10],
+    #[doc = "0x20 - Clock Gating Configure Register"]
+    pub clock_gate: CLOCK_GATE,
+    #[doc = "0x24 - MISC Register"]
+    pub sigmadelta_misc: SIGMADELTA_MISC,
+    #[doc = "0x28 - PAD Compare configure Register"]
+    pub pad_comp_config: PAD_COMP_CONFIG,
+    #[doc = "0x2c - Zero Detect filter Register"]
+    pub pad_comp_filter: PAD_COMP_FILTER,
+    #[doc = "0x30..0x50 - Glitch Filter Configure Register of Channel%s"]
+    pub glitch_filter_ch: [GLITCH_FILTER_CH; 8],
+    _reserved6: [u8; 0x10],
+    #[doc = "0x60..0x80 - Etm Config register of Channel%s"]
+    pub etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8],
+    _reserved7: [u8; 0x20],
+    #[doc = "0xa0 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p0_cfg: ETM_TASK_P0_CFG,
+    #[doc = "0xa4 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p1_cfg: ETM_TASK_P1_CFG,
+    #[doc = "0xa8 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p2_cfg: ETM_TASK_P2_CFG,
+    #[doc = "0xac - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p3_cfg: ETM_TASK_P3_CFG,
+    #[doc = "0xb0 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p4_cfg: ETM_TASK_P4_CFG,
+    #[doc = "0xb4 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p5_cfg: ETM_TASK_P5_CFG,
+    #[doc = "0xb8 - Etm Configure Register to decide which GPIO been chosen"]
+    pub etm_task_p6_cfg: ETM_TASK_P6_CFG,
+    _reserved14: [u8; 0x24],
+    #[doc = "0xe0 - GPIOSD interrupt raw register"]
+    pub int_raw: INT_RAW,
+    #[doc = "0xe4 - GPIOSD interrupt masked register"]
+    pub int_st: INT_ST,
+    #[doc = "0xe8 - GPIOSD interrupt enable register"]
+    pub int_ena: INT_ENA,
+    #[doc = "0xec - GPIOSD interrupt clear register"]
+    pub int_clr: INT_CLR,
+    _reserved18: [u8; 0x0c],
+    #[doc = "0xfc - Version Control Register"]
+    pub version: VERSION,
+}
+#[doc = "SIGMADELTA (rw) register accessor: Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sigmadelta`] module"]
+pub type SIGMADELTA = crate::Reg<sigmadelta::SIGMADELTA_SPEC>;
+#[doc = "Duty Cycle Configure Register of SDM%s"]
+pub mod sigmadelta;
+#[doc = "CLOCK_GATE (rw) register accessor: Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clock_gate`] module"]
+pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
+#[doc = "Clock Gating Configure Register"]
+pub mod clock_gate;
+#[doc = "SIGMADELTA_MISC (rw) register accessor: MISC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta_misc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sigmadelta_misc`] module"]
+pub type SIGMADELTA_MISC = crate::Reg<sigmadelta_misc::SIGMADELTA_MISC_SPEC>;
+#[doc = "MISC Register"]
+pub mod sigmadelta_misc;
+#[doc = "PAD_COMP_CONFIG (rw) register accessor: PAD Compare configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pad_comp_config`] module"]
+pub type PAD_COMP_CONFIG = crate::Reg<pad_comp_config::PAD_COMP_CONFIG_SPEC>;
+#[doc = "PAD Compare configure Register"]
+pub mod pad_comp_config;
+#[doc = "PAD_COMP_FILTER (rw) register accessor: Zero Detect filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_filter::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_filter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pad_comp_filter`] module"]
+pub type PAD_COMP_FILTER = crate::Reg<pad_comp_filter::PAD_COMP_FILTER_SPEC>;
+#[doc = "Zero Detect filter Register"]
+pub mod pad_comp_filter;
+#[doc = "GLITCH_FILTER_CH (rw) register accessor: Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glitch_filter_ch::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glitch_filter_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`glitch_filter_ch`] module"]
+pub type GLITCH_FILTER_CH = crate::Reg<glitch_filter_ch::GLITCH_FILTER_CH_SPEC>;
+#[doc = "Glitch Filter Configure Register of Channel%s"]
+pub mod glitch_filter_ch;
+#[doc = "ETM_EVENT_CH_CFG (rw) register accessor: Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_event_ch_cfg`] module"]
+pub type ETM_EVENT_CH_CFG = crate::Reg<etm_event_ch_cfg::ETM_EVENT_CH_CFG_SPEC>;
+#[doc = "Etm Config register of Channel%s"]
+pub mod etm_event_ch_cfg;
+#[doc = "ETM_TASK_P0_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p0_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p0_cfg`] module"]
+pub type ETM_TASK_P0_CFG = crate::Reg<etm_task_p0_cfg::ETM_TASK_P0_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p0_cfg;
+#[doc = "ETM_TASK_P1_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p1_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p1_cfg`] module"]
+pub type ETM_TASK_P1_CFG = crate::Reg<etm_task_p1_cfg::ETM_TASK_P1_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p1_cfg;
+#[doc = "ETM_TASK_P2_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p2_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p2_cfg`] module"]
+pub type ETM_TASK_P2_CFG = crate::Reg<etm_task_p2_cfg::ETM_TASK_P2_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p2_cfg;
+#[doc = "ETM_TASK_P3_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p3_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p3_cfg`] module"]
+pub type ETM_TASK_P3_CFG = crate::Reg<etm_task_p3_cfg::ETM_TASK_P3_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p3_cfg;
+#[doc = "ETM_TASK_P4_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p4_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p4_cfg`] module"]
+pub type ETM_TASK_P4_CFG = crate::Reg<etm_task_p4_cfg::ETM_TASK_P4_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p4_cfg;
+#[doc = "ETM_TASK_P5_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p5_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p5_cfg`] module"]
+pub type ETM_TASK_P5_CFG = crate::Reg<etm_task_p5_cfg::ETM_TASK_P5_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p5_cfg;
+#[doc = "ETM_TASK_P6_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p6_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p6_cfg`] module"]
+pub type ETM_TASK_P6_CFG = crate::Reg<etm_task_p6_cfg::ETM_TASK_P6_CFG_SPEC>;
+#[doc = "Etm Configure Register to decide which GPIO been chosen"]
+pub mod etm_task_p6_cfg;
+#[doc = "INT_RAW (r) register accessor: GPIOSD interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_raw`] module"]
+pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
+#[doc = "GPIOSD interrupt raw register"]
+pub mod int_raw;
+#[doc = "INT_ST (r) register accessor: GPIOSD interrupt masked register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_st`] module"]
+pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
+#[doc = "GPIOSD interrupt masked register"]
+pub mod int_st;
+#[doc = "INT_ENA (rw) register accessor: GPIOSD interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_ena`] module"]
+pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
+#[doc = "GPIOSD interrupt enable register"]
+pub mod int_ena;
+#[doc = "INT_CLR (w) register accessor: GPIOSD interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
+#[doc = "GPIOSD interrupt clear register"]
+pub mod int_clr;
+#[doc = "VERSION (rw) register accessor: Version Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`version`] module"]
+pub type VERSION = crate::Reg<version::VERSION_SPEC>;
+#[doc = "Version Control Register"]
+pub mod version;

esp32h2/src/gpio_sd/clock_gate.rs

@@ -0,0 +1,59 @@
+#[doc = "Register `CLOCK_GATE` reader"]
+pub type R = crate::R<CLOCK_GATE_SPEC>;
+#[doc = "Register `CLOCK_GATE` writer"]
+pub type W = crate::W<CLOCK_GATE_SPEC>;
+#[doc = "Field `CLK_EN` reader - Clock enable bit of configuration registers for sigma delta modulation."]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - Clock enable bit of configuration registers for sigma delta modulation."]
+pub type CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+impl R {
+    #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLOCK_GATE")
+            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        self.read().fmt(f)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."]
+    #[inline(always)]
+    #[must_use]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC, 0> {
+        CLK_EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLOCK_GATE_SPEC;
+impl crate::RegisterSpec for CLOCK_GATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
+impl crate::Readable for CLOCK_GATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
+impl crate::Writable for CLOCK_GATE_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets CLOCK_GATE to value 0"]
+impl crate::Resettable for CLOCK_GATE_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}