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[hw,ibex,rtl] Add DFT response signals to caches
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Signed-off-by: Andreas Kurth <adk@lowrisc.org>
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@andreaskurth
andreaskurth committed Dec 24, 2024
1 parent 5b8c392 commit bdeb890
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Showing 11 changed files with 852 additions and 214 deletions.
33 changes: 32 additions & 1 deletion hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
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Expand Up @@ -69,11 +69,34 @@

{ struct: "ram_1p_cfg",
type: "uni",
name: "ram_cfg",
name: "ram_cfg_icache_tag",
act: "rcv",
package: "prim_ram_1p_pkg",
},

{ struct: "ram_1p_cfg_rsp",
type: "uni",
name: "ram_cfg_rsp_icache_tag",
width: "ICacheNWays",
act: "req",
package: "prim_ram_1p_pkg",
},

{ struct: "ram_1p_cfg",
type: "uni",
name: "ram_cfg_icache_data",
act: "rcv",
package: "prim_ram_1p_pkg",
},

{ struct: "ram_1p_cfg_rsp",
type: "uni",
name: "ram_cfg_rsp_icache_data",
width: "ICacheNWays",
act: "req",
package: "prim_ram_1p_pkg",
},

{ struct: "logic",
type: "uni",
name: "hart_id",
Expand Down Expand Up @@ -367,6 +390,14 @@
expose: "true"
},

{ name: "ICacheNWays"
type: "int unsigned"
default: "2"
desc: "Number of instruction cache ways"
local: "true"
expose: "true"
},

{ name: "BranchPredictor"
type: "bit"
default: "0"
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49 changes: 26 additions & 23 deletions hw/ip/rv_core_ibex/doc/interfaces.md
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Expand Up @@ -13,29 +13,32 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------|:---------------------------------|:--------|:------|--------:|:--------------|
| rst_cpu_n | logic | uni | req | 1 | |
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| hart_id | logic | uni | rcv | 32 | |
| boot_addr | logic | uni | rcv | 32 | |
| irq_software | logic | uni | rcv | 1 | |
| irq_timer | logic | uni | rcv | 1 | |
| irq_external | logic | uni | rcv | 1 | |
| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
| debug_req | logic | uni | rcv | 1 | |
| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | |
| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | |
| nmi_wdog | logic | uni | rcv | 1 | |
| edn | edn_pkg::edn | req_rsp | req | 1 | |
| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | |
| fpga_info | logic | uni | rcv | 32 | |
| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:------------------------|:---------------------------------|:--------|:------|:------------|:--------------|
| rst_cpu_n | logic | uni | req | 1 | |
| ram_cfg_icache_tag | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp_icache_tag | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | |
| ram_cfg_icache_data | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp_icache_data | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | |
| hart_id | logic | uni | rcv | 32 | |
| boot_addr | logic | uni | rcv | 32 | |
| irq_software | logic | uni | rcv | 1 | |
| irq_timer | logic | uni | rcv | 1 | |
| irq_external | logic | uni | rcv | 1 | |
| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
| debug_req | logic | uni | rcv | 1 | |
| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | |
| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | |
| nmi_wdog | logic | uni | rcv | 1 | |
| edn | edn_pkg::edn | req_rsp | req | 1 | |
| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | |
| fpga_info | logic | uni | rcv | 32 | |
| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Security Alerts

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13 changes: 11 additions & 2 deletions hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ module rv_core_ibex
parameter bit ICache = 1'b1,
parameter bit ICacheECC = 1'b1,
parameter bit ICacheScramble = 1'b1,
parameter int unsigned ICacheNWays = 2,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b1,
parameter int unsigned DbgHwBreakNum = 4,
Expand Down Expand Up @@ -60,7 +61,10 @@ module rv_core_ibex
// Reset feedback to rstmgr
output logic rst_cpu_n_o,

input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ICacheNWays-1:0] ram_cfg_rsp_icache_tag_o,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ICacheNWays-1:0] ram_cfg_rsp_icache_data_o,

input logic [31:0] hart_id_i,
input logic [31:0] boot_addr_i,
Expand Down Expand Up @@ -423,7 +427,10 @@ module rv_core_ibex
.test_en_i (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)),
.scan_rst_ni,

.ram_cfg_i,
.ram_cfg_icache_tag_i,
.ram_cfg_rsp_icache_tag_o,
.ram_cfg_icache_data_i,
.ram_cfg_rsp_icache_data_o,

.hart_id_i,
.boot_addr_i,
Expand Down Expand Up @@ -907,6 +914,8 @@ module rv_core_ibex
.tl_h_o(tl_win_d2h_err_rsp)
);

`ASSERT_INIT(ICacheNWaysCorrect_A, ICacheNWays == ibex_pkg::IC_NUM_WAYS)

// Assertions for CPU enable
// Allow 2 or 3 cycles for input to enable due to synchronizers
`ASSERT(FpvSecCmIbexFetchEnable0_A,
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182 changes: 179 additions & 3 deletions hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -8990,6 +8990,15 @@
expose: "true"
name_top: RvCoreIbexICacheScramble
}
{
name: ICacheNWays
desc: Number of instruction cache ways
type: int unsigned
default: 2
local: "true"
expose: "true"
name_top: RvCoreIbexICacheNWays
}
{
name: BranchPredictor
desc: Branch predictor
Expand Down Expand Up @@ -9084,7 +9093,7 @@
index: -1
}
{
name: ram_cfg
name: ram_cfg_icache_tag
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
Expand All @@ -9095,6 +9104,66 @@
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: ram_cfg_rsp_icache_tag
struct: ram_1p_cfg_rsp
package: prim_ram_1p_pkg
type: uni
act: req
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
inst_name: rv_core_ibex
default: ""
external: true
top_signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp
conn_type: false
index: -1
}
{
name: ram_cfg_icache_data
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: ram_cfg_rsp_icache_data
struct: ram_1p_cfg_rsp
package: prim_ram_1p_pkg
type: uni
act: req
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
inst_name: rv_core_ibex
default: ""
external: true
top_signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp
conn_type: false
index: -1
}
{
name: hart_id
struct: logic
Expand Down Expand Up @@ -9472,7 +9541,8 @@
sram_ctrl_main.cfg
sram_ctrl_ret_aon.cfg
sram_ctrl_mbox.cfg
rv_core_ibex.ram_cfg
rv_core_ibex.ram_cfg_icache_tag
rv_core_ibex.ram_cfg_icache_data
]
ast.spi_ram_2p_cfg:
[
Expand Down Expand Up @@ -10122,6 +10192,8 @@
sram_ctrl_mbox.cfg_rsp: sram_ctrl_mbox_ram_1p_cfg_rsp
otbn.ram_cfg_rsp_imem: otbn_imem_ram_1p_cfg_rsp
otbn.ram_cfg_rsp_dmem: otbn_dmem_ram_1p_cfg_rsp
rv_core_ibex.ram_cfg_rsp_icache_tag: rv_core_ibex_icache_tag_ram_1p_cfg_rsp
rv_core_ibex.ram_cfg_rsp_icache_data: rv_core_ibex_icache_data_ram_1p_cfg_rsp
spi_device.ram_cfg_rsp_sys2spi: spi_device_ram_2p_cfg_rsp_sys2spi
spi_device.ram_cfg_rsp_spi2sys: spi_device_ram_2p_cfg_rsp_spi2sys
pwrmgr_aon.boot_status: pwrmgr_boot_status
Expand Down Expand Up @@ -23099,7 +23171,7 @@
index: -1
}
{
name: ram_cfg
name: ram_cfg_icache_tag
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
Expand All @@ -23110,6 +23182,66 @@
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: ram_cfg_rsp_icache_tag
struct: ram_1p_cfg_rsp
package: prim_ram_1p_pkg
type: uni
act: req
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
inst_name: rv_core_ibex
default: ""
external: true
top_signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp
conn_type: false
index: -1
}
{
name: ram_cfg_icache_data
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: ram_cfg_rsp_icache_data
struct: ram_1p_cfg_rsp
package: prim_ram_1p_pkg
type: uni
act: req
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
inst_name: rv_core_ibex
default: ""
external: true
top_signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp
conn_type: false
index: -1
}
{
name: hart_id
struct: logic
Expand Down Expand Up @@ -24651,6 +24783,50 @@
index: -1
netname: otbn_dmem_ram_1p_cfg_rsp
}
{
package: prim_ram_1p_pkg
struct: ram_1p_cfg_rsp
signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: rv_core_ibex_icache_tag_ram_1p_cfg_rsp
}
{
package: prim_ram_1p_pkg
struct: ram_1p_cfg_rsp
signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp_o
width:
{
name: ICacheNWays
desc: Number of instruction cache ways
param_type: int unsigned
unpacked_dimensions: null
default: 2
local: true
expose: true
name_top: RvCoreIbexICacheNWays
}
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: rv_core_ibex_icache_data_ram_1p_cfg_rsp
}
{
package: prim_ram_2p_pkg
struct: ram_2p_cfg
Expand Down
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