[nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration

drivers/pinctrl/pinctrl_nrf.c

@@ -94,6 +94,15 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
 #endif
 
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE)
+#define NRF_PSEL_SDP_MSPI(reg, pin)                                                                \
+	((NRF_GPIO_Type *)reg)->PIN_CNF[pin] =                                                     \
+		((((NRF_GPIO_Type *)reg)->PIN_CNF[pin] & ~GPIO_PIN_CNF_CTRLSEL_Msk) |              \
+		 (NRF_GPIO_PIN_SEL_VPR << GPIO_PIN_CNF_CTRLSEL_Pos));
+#endif
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
@@ -347,6 +356,25 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_CONNECT;
 			break;
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
+		case NRF_FUN_SDP_MSPI_CS0:
+		case NRF_FUN_SDP_MSPI_CS1:
+		case NRF_FUN_SDP_MSPI_SCK:
+		case NRF_FUN_SDP_MSPI_DQ0:
+		case NRF_FUN_SDP_MSPI_DQ1:
+		case NRF_FUN_SDP_MSPI_DQ2:
+		case NRF_FUN_SDP_MSPI_DQ3:
+		case NRF_FUN_SDP_MSPI_DQ4:
+		case NRF_FUN_SDP_MSPI_DQ5:
+		case NRF_FUN_SDP_MSPI_DQ6:
+		case NRF_FUN_SDP_MSPI_DQ7:
+			NRF_PSEL_SDP_MSPI(reg, psel);
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */
+#endif /* CONFIG_SOC_NRF54L15_CPUAPP */
 		default:
 			return -ENOTSUP;
 		}
@@ -380,8 +408,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
 			}
 
-			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
-				     drive, NRF_GPIO_PIN_NOSENSE);
+			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]), drive,
+				     NRF_GPIO_PIN_NOSENSE);
 #if NRF_GPIO_HAS_CLOCKPIN
 			nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
 #endif

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

@@ -162,6 +162,28 @@
 #define NRF_FUN_CAN_TX 46U
 /** CAN RX */
 #define NRF_FUN_CAN_RX 47U
+/** SDP_MSPI CK */
+#define NRF_FUN_SDP_MSPI_SCK 48U
+/** SDP_MSPI DQ0 */
+#define NRF_FUN_SDP_MSPI_DQ0 49U
+/** SDP_MSPI DQ1 */
+#define NRF_FUN_SDP_MSPI_DQ1 50U
+/** SDP_MSPI DQ2 */
+#define NRF_FUN_SDP_MSPI_DQ2 51U
+/** SDP_MSPI DQ3 */
+#define NRF_FUN_SDP_MSPI_DQ3 52U
+/** SDP_MSPI DQ4 */
+#define NRF_FUN_SDP_MSPI_DQ4 53U
+/** SDP_MSPI DQ5 */
+#define NRF_FUN_SDP_MSPI_DQ5 54U
+/** SDP_MSPI DQ6 */
+#define NRF_FUN_SDP_MSPI_DQ6 55U
+/** SDP_MSPI DQ7 */
+#define NRF_FUN_SDP_MSPI_DQ7 56U
+/** SDP_MSPI CS0 */
+#define NRF_FUN_SDP_MSPI_CS0 57U
+/** SDP_MSPI CS1 */
+#define NRF_FUN_SDP_MSPI_CS1 58U
 
 /** @} */
 

modules/hal_nordic/nrfx/nrfe_config.h

@@ -9,6 +9,8 @@
 
 #ifdef CONFIG_GPIO_NRFE
 #include <drivers/gpio/nrfe_gpio.h>
+#elif CONFIG_MSPI_NRFE
+#include <drivers/mspi/nrfe_mspi.h>
 #else
 #error "NRFE config header included, even though no SW-define IO device is enabled."
 #endif

tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ / {
+	aliases {
+		mspi0 = &sdp_mspi;
+	};
+};
+
+&cpuflpr_vpr {
+	status = "okay";
+
+	sdp_mspi: sdp_mspi@5004c000 {
+		mspi_device: mspi_device@0 {
+			status = "okay";
+			compatible = "zephyr,mspi-emul-device";
+			reg = <0x0>;
+			mspi-max-frequency = <48000000>;
+		};
+	};
+};

tests/drivers/mspi/api/src/main.c

@@ -20,7 +20,11 @@
 typedef enum mspi_ambiq_timing_param mspi_timing_param;
 #endif
 
+// #if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+// #define MSPI_BUS_NODE       DT_NODELABEL(sdp_mspi)
+// #else
 #define MSPI_BUS_NODE       DT_ALIAS(mspi0)
+// #endif
 
 static const struct device *mspi_devices[] = {
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, DEVICE_DT_GET, (,))
@@ -51,13 +55,17 @@
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_DEVICE_CONFIG_DT, (,))
 };
 
+#if CONFIG_MSPI_XIP
 static struct mspi_xip_cfg xip_cfg[] = {
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_XIP_CONFIG_DT, (,))
 };
+#endif
 
+#if CONFIG_MSPI_SCRAMBLE
 static struct mspi_scramble_cfg scramble_cfg[] = {
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_SCRAMBLE_CONFIG_DT, (,))
 };
+#endif
 
 ZTEST(mspi_api, test_mspi_api)
 {
@@ -102,9 +110,11 @@
 		zassert_equal(ret, 0, "mspi_timing_config failed.");
 #endif
 
+#if CONFIG_MSPI_ASYNC
 		ret = mspi_register_callback(mspi_bus, &dev_id[dev_idx],
 					     MSPI_BUS_XFER_COMPLETE, NULL, NULL);
 		zassert_equal(ret, 0, "mspi_register_callback failed.");
+#endif
 
 		ret = mspi_get_channel_status(mspi_bus, 0);
 		zassert_equal(ret, 0, "mspi_get_channel_status failed.");

tests/drivers/mspi/api/testcase.yaml

@@ -15,3 +15,19 @@ tests:
       - apollo3p_evb
     integration_platforms:
       - native_sim
+
+  drivers.mspi.api.emspi:
+    tags:
+      - drivers
+      - mspi
+      - api
+    harness: ztest
+    platform_allow:
+      - nrf54l15dk_nrf54l15_cpuapp
+    integration_platforms:
+      - nrf54l15dk_nrf54l15_cpuapp
+    extra_args:
+      - SB_CONFIG_VPR_LAUNCHER=n
+      - SB_CONFIG_PARTITION_MANAGER=n
+      - SB_CONFIG_SDP=y
+      - SB_CONFIG_SDP_MSPI=y