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Merge master into develop [DO NOT MERGE - only to see the diff] #2869

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wants to merge 4,636 commits into from
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Merge master into develop [DO NOT MERGE - only to see the diff] #2869

wants to merge 4,636 commits into from

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dannywillems
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dannywillems and others added 30 commits November 4, 2024 11:37
@dannywillems
o1vm/riscv32i: introduce SCRATCH_SIZE and column module
2d222e6
@dannywillems
o1vm/riscv32i: introduce column module and instruction set size
89d9af9
@dannywillems
o1vm/riscv32i: start add instruction list
046a89a
@dannywillems
o1vm/riscv32i: some more instructions
51f1a5f
@dannywillems
o1vm/riscv32i: split and add the different instructions
e646c61 
Based on https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf
@svv232 @dannywillems
extending Itype definitions with Load instructsions
7a21ef7
@svv232 @dannywillems
adding xori and formatting
46c328f
@svv232 @dannywillems
adding or immediate and changing instruction order to match spec
7a74b6e
@dannywillems
o1vm/riscv32i: implement iterator over the instructions
c315337
@svv232 @dannywillems
renaming jump link register function, refactoring jinst to ujinst to …
941d9ac 
…match the spec, and adding support for uj instructions
@svv232 @dannywillems
changing btype to sbtype to match the spec
66709e0
@svv232 @dannywillems
added support for fence instructions and all of the rtype instructions
e6e2a49
@dannywillems
o1vm/riscv32i: reimplement display to get the string repr
7d1f7f3
@dannywillems
o1vm/riscv32i: test correctly the to_string method
536cbcb
@dannywillems
o1vm/riscv32i: define interpreter interface
72a8843
@dannywillems
o1vm/riscv32i: sketch the witness environment
0b02dda
@dannywillems
o1vm/riscv32i: implement constraints environment
692acab
@dannywillems
o1vm/riscv32i: split interpret_instruction in subroutines
9c481e9
@svv232
adding boilerplate for syscall instruction type without impl i.e exte…
d18fdd9 
…nding the iterator in the interpreter and adding to the column type
@svv232
adding memory constants for the interpreter
e737bd3
@svv232
create interpreter implementation and adding instruction decoder
35796f7
@svv232
correcting instruction decoding to follow spec
47eacb0
@svv232
correcting more instruction implementations in display
7e6756f
@svv232
adding step function and test_no_action test
359d565
@svv232
fixing imports and removing tests so o1vmtest can be imported in the …
c94c9f2 
…next sequence of changes
@svv232
adding no action binary from o1vm test, implementing i iinstruction a…
757751b 
…nd single syscall
@svv232
reformat import in test
0681bf0
@dannywillems
Merge pull request #2741 from o1-labs/dw/simple-elf-loader
103513f 
o1vm: implement a simple ELF loader
@dannywillems
Merge pull request #2742 from o1-labs/dw/update-o1vm-description
d6a1178 
o1vm: update description
@dannywillems
Merge pull request #2743 from o1-labs/dw/o1vm-riscv32i-add-registers
998c794 
o1vm/riscv32i: define registers
dannywillems and others added 28 commits December 3, 2024 16:32
@dannywillems
Merge pull request #2807 from o1-labs/dw/riscv32-impl-m-type-divu
8da1a41 
o1vm/riscv32: implement M type instruction divu
@dannywillems
Merge pull request #2808 from o1-labs/dw/riscv32-impl-m-type-remu
31a9b3f 
o1vm/riscv32: implement M type instruction Remu
@dannywillems
Merge pull request #2809 from o1-labs/dw/riscv32-impl-mul-hi-signed-u…
71d6a09 
…nsigned

o1vm/riscv32: implement mul_hi_signed_unsigned to be used for Mulhsu
@dannywillems
o1vm/riscv32: implement M type instruction Mulhsu
277cec8
@dannywillems
Merge pull request #2810 from o1-labs/dw/riscv32-impl-mulhsu
d0f9cb3 
o1vm/riscv32: implement M type instruction Mulhsu
@dannywillems
o1vm/riscv32im: improve documentation reg. semantic of op
54edc55
@dannywillems
o1vm/riscv32im: add semantic for MInstruction
964cfeb
@dannywillems
Merge pull request #2817 from o1-labs/dw/riscv32im-add-semantic-impl
3589aed 
o1vm/riscv32im: add documentation reg. semantic of instructions
@dannywillems
Merge branch 'master' into o1vm/riscv32im/test-decoding-add
0917d01
@dannywillems
CI/o1vm: deactivating path dependent execution
673954a 
As we enforce some GH actions to pass when targeting master, it can make PR
stalled and unmergeable. I do not see any options in GH settings at the moment
to include these conditions.
@dannywillems
Merge pull request #2819 from o1-labs/o1vm/riscv32im/test-decoding-add
e1875cf 
o1vm/riscv32im: test decoding add
@dannywillems
Merge branch 'master' into o1vm/riscv32im/test-decoding-sub
ea5cb0e
@dannywillems
Merge pull request #2863 from o1-labs/ci/deactivate-conditional-actions
a58943d 
CI/o1vm: deactivating path dependent execution
@dannywillems
Mina-signer: make secret field of KeyPair public
9b2ad57
@dannywillems
Merge pull request #2820 from o1-labs/o1vm/riscv32im/test-decoding-sub
55c51b3 
o1vm/riscv32im: test decoding sub
@dannywillems
Merge branch 'master' into o1vm/riscv32im/test-decoding-sll
e0b822f
@dannywillems
Merge pull request #2755 from o1-labs/dw/make-secret-field-public-min…
abc1bbb 
…a-signer

Mina-signer: make secret field of KeyPair public
@dannywillems
Merge pull request #2821 from o1-labs/o1vm/riscv32im/test-decoding-sll
388aaf0 
o1vm/riscv32im: test decoding sll
@dannywillems
Merge pull request #2822 from o1-labs/o1vm/riscv32im/test-decoding-slt
0116f6c 
o1vm/riscv32im: test decoding slt
@dannywillems
Merge pull request #2823 from o1-labs/o1vm/riscv32im/test-decoding-sltu
f25d9d5 
o1vm/riscv32im: test decoding sltu
@dannywillems
Merge pull request #2824 from o1-labs/o1vm/riscv32im/test-decoding-xor
55e9941 
o1vm/riscv32im: test decoding xor
@dannywillems
Merge pull request #2825 from o1-labs/o1vm/riscv32im/test-decoding-srl
2c002d6 
o1vm/riscv32im: test decoding srl
@dannywillems
Merge pull request #2826 from o1-labs/o1vm/riscv32im/test-decoding-sra
26fc376 
o1vm/riscv32im: test decoding sra
@dannywillems
Merge pull request #2828 from o1-labs/o1vm/riscv32im/test-decoding-or
25447f6 
o1vm/riscv32im: test decoding or
@dannywillems
Merge pull request #2830 from o1-labs/o1vm/riscv32im/test-decoding-and
578d17c 
o1vm/riscv32im: test decoding and
@dannywillems
Merge pull request #2849 from o1-labs/o1vm/deps-reorg
0af1256 
o1vm: reorganize dependencies in alphabetical order [no-op]
@martyall
self helping Makefile
98e7c35
@dannywillems
Merge pull request #2867 from o1-labs/martin/add-make-help
cdbc90c 
Improve your Makefile with this one neat trick
@dannywillems
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Closing. Was only for the diff on GH.

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4 participants
@dannywillems @svv232 @volhovm @martyall