Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merge master into develop [DO NOT MERGE - only to see the diff] #2869

Closed
wants to merge 4,636 commits into from
Closed
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4636 commits
Select commit Hold shift + click to select a range
2d222e6
o1vm/riscv32i: introduce SCRATCH_SIZE and column module
dannywillems Nov 4, 2024
89d9af9
o1vm/riscv32i: introduce column module and instruction set size
dannywillems Nov 4, 2024
046a89a
o1vm/riscv32i: start add instruction list
dannywillems Oct 22, 2024
51f1a5f
o1vm/riscv32i: some more instructions
dannywillems Oct 22, 2024
e646c61
o1vm/riscv32i: split and add the different instructions
dannywillems Oct 22, 2024
7a21ef7
extending Itype definitions with Load instructsions
svv232 Oct 22, 2024
46c328f
adding xori and formatting
svv232 Oct 22, 2024
7a74b6e
adding or immediate and changing instruction order to match spec
svv232 Oct 22, 2024
c315337
o1vm/riscv32i: implement iterator over the instructions
dannywillems Oct 22, 2024
941d9ac
renaming jump link register function, refactoring jinst to ujinst to …
svv232 Oct 23, 2024
66709e0
changing btype to sbtype to match the spec
svv232 Oct 23, 2024
e6e2a49
added support for fence instructions and all of the rtype instructions
svv232 Oct 23, 2024
7d1f7f3
o1vm/riscv32i: reimplement display to get the string repr
dannywillems Oct 27, 2024
536cbcb
o1vm/riscv32i: test correctly the to_string method
dannywillems Oct 27, 2024
72a8843
o1vm/riscv32i: define interpreter interface
dannywillems Nov 4, 2024
0b02dda
o1vm/riscv32i: sketch the witness environment
dannywillems Nov 4, 2024
692acab
o1vm/riscv32i: implement constraints environment
dannywillems Nov 4, 2024
9c481e9
o1vm/riscv32i: split interpret_instruction in subroutines
dannywillems Nov 4, 2024
d18fdd9
adding boilerplate for syscall instruction type without impl i.e exte…
svv232 Nov 12, 2024
e737bd3
adding memory constants for the interpreter
svv232 Nov 12, 2024
35796f7
create interpreter implementation and adding instruction decoder
svv232 Nov 12, 2024
47eacb0
correcting instruction decoding to follow spec
svv232 Nov 12, 2024
7e6756f
correcting more instruction implementations in display
svv232 Nov 12, 2024
359d565
adding step function and test_no_action test
svv232 Nov 12, 2024
c94c9f2
fixing imports and removing tests so o1vmtest can be imported in the …
svv232 Nov 12, 2024
757751b
adding no action binary from o1vm test, implementing i iinstruction a…
svv232 Nov 12, 2024
0681bf0
reformat import in test
svv232 Nov 12, 2024
103513f
Merge pull request #2741 from o1-labs/dw/simple-elf-loader
dannywillems Nov 14, 2024
d6a1178
Merge pull request #2742 from o1-labs/dw/update-o1vm-description
dannywillems Nov 14, 2024
998c794
Merge pull request #2743 from o1-labs/dw/o1vm-riscv32i-add-registers
dannywillems Nov 14, 2024
4c8dcde
Merge pull request #2744 from o1-labs/dw/o1vm-move-memory-size-top-le…
dannywillems Nov 14, 2024
81872e2
Merge pull request #2745 from o1-labs/dw/o1vm-riscv32i-introduce-scra…
dannywillems Nov 14, 2024
362155c
Merge pull request #2746 from o1-labs/dw/o1vm-riscv32i-instruction-set
dannywillems Nov 14, 2024
af20066
Merge pull request #2747 from o1-labs/dw/interpreter-constraint-witne…
dannywillems Nov 14, 2024
c38c88e
Merge pull request #2748 from o1-labs/dw/split-interpret-instruction-…
dannywillems Nov 14, 2024
5b6d530
Merge pull request #2751 from o1-labs/sai/syscall-interpret-instructi…
dannywillems Nov 14, 2024
fe68e1c
Merge pull request #2752 from o1-labs/sai/memory-constants-riscv32
dannywillems Nov 14, 2024
59250e7
Merge pull request #2753 from o1-labs/sai/instruction-decoding-riscv32
dannywillems Nov 14, 2024
f58bdb3
Merge remote-tracking branch 'origin/master' into sai/adding-test-no-…
svv232 Nov 18, 2024
e922e90
Update o1vm/src/interpreters/riscv32i/interpreter.rs
svv232 Nov 18, 2024
4bc0b20
setting instruction count to the current number of instruction values…
svv232 Nov 18, 2024
3fdda8e
add elf parser test
svv232 Nov 18, 2024
119b5a1
Merge pull request #2754 from o1-labs/sai/adding-test-no-action
svv232 Nov 18, 2024
b8f4065
RISC-V32: aesthetic
dannywillems Nov 19, 2024
ac91cfe
RISC-V32: sketch support for M types
dannywillems Nov 19, 2024
fe054c8
o1vm: rename riscv32i in riscv32im
dannywillems Nov 19, 2024
241a86b
o1vm/ELF: rename parse_riscv32i in parse_riscv32
dannywillems Nov 19, 2024
0249bbc
Merge pull request #2762 from o1-labs/dw/riscv32-support-m
dannywillems Nov 20, 2024
20b9a59
o1vm/riscv32im: add more documentation reg. instructions
dannywillems Nov 20, 2024
8a2d818
o1vm/riscv32: rename resources directory into riscv32im
dannywillems Nov 20, 2024
3567e9a
o1vm/riscv32: introduce is_prime_naive binary to test remu
dannywillems Nov 20, 2024
70680c8
o1vm/riscv32: remove (commented) code related to debugging
dannywillems Nov 20, 2024
d23b729
o1vm/interpreter: sketch interpret_rtype, add documentation
svv232 Nov 20, 2024
e0dbf60
Merge pull request #2763 from o1-labs/dw/o1vm-document-instr
dannywillems Nov 20, 2024
18aa79c
o1vm/riscv32: implement R type instruction add
svv232 Nov 20, 2024
298f4cb
o1vm/riscv32: implement sub
svv232 Nov 20, 2024
6ec50cd
o1vm/riscv32: implement R type instruction sll
svv232 Nov 20, 2024
c9a507d
o1vm/riscv32: implement R type instruction slt
svv232 Nov 20, 2024
2e9ecdd
o1vm/riscv32: implement R type instruction sltu
svv232 Nov 20, 2024
3400ff0
o1vm/riscv32: implement R type instruction xor
svv232 Nov 20, 2024
75327ec
o1vm/riscv32: implement R type instruction srl
svv232 Nov 20, 2024
07e58b6
o1vm/riscv32: implement R type instruction sra
svv232 Nov 20, 2024
b403ffd
o1vm/riscv32: implement R type instruction or
svv232 Nov 20, 2024
50a5f44
o1vm/riscv32: implement R type instruction and
svv232 Nov 20, 2024
7672036
o1vm/riscv32: add documentation to interpret_itype
dannywillems Nov 20, 2024
baf6e03
o1vm/riscv32: remove doc as code follows the codebase convention
dannywillems Nov 20, 2024
e592318
o1vm/riscv32: add decoding constraint
dannywillems Nov 20, 2024
6dc8da5
o1vm/riscv32: sketch implementation of S-type instr interpretation
svv232 Nov 20, 2024
647bab7
o1vm/riscv32: header to riscv32im + credits
dannywillems Nov 20, 2024
8d106ba
o1vm/riscv32: modestly improve documentation + rendering
dannywillems Nov 20, 2024
25c2e8d
Merge pull request #2765 from o1-labs/dw/o1vm/rename-resources-directory
dannywillems Nov 20, 2024
436d921
o1vm/riscv32: sketch implementation of SB-type instr interpretation
svv232 Nov 20, 2024
5057235
Merge pull request #2766 from o1-labs/dw/o1vm/add-is-prime-naive-bina…
dannywillems Nov 20, 2024
ad15049
o1vm/riscv32: sketch implementation of U-type instr interpretation
svv232 Nov 20, 2024
36c498e
o1vm/riscv32: add empty line for better rendering
dannywillems Nov 20, 2024
eb74eb0
o1vm/riscv32: sketch implementation of UJ-type instr interpretation
svv232 Nov 20, 2024
63e8387
o1vm/riscv32: expand missing instructions for itype
dannywillems Nov 20, 2024
2d9bc05
o1vm/riscv32: add fibonacci-7 test, and ignore it for now
svv232 Nov 20, 2024
595dbf4
o1vm/riscv32: sketch interpretation of mtype instruction
dannywillems Nov 20, 2024
203e376
Merge pull request #2767 from o1-labs/dw/o1vm/remove-debugging-commen…
dannywillems Nov 20, 2024
ef8f7c6
o1vm/mips: move regtest reg. number of selectors into MIPS directory
dannywillems Nov 20, 2024
370e099
o1vm/riscv32: introduce tests checking the number of instructions
dannywillems Nov 20, 2024
c58cd7f
Merge pull request #2768 from o1-labs/dw/interpret-rtype-import
dannywillems Nov 20, 2024
1992ca9
Merge pull request #2769 from o1-labs/dw/implement-add-riscv32
dannywillems Nov 20, 2024
58fbae4
Merge pull request #2770 from o1-labs/dw/implement-sub-riscv32
dannywillems Nov 20, 2024
0bcde57
o1vm/riscv32: implement mul_hi_signed
dannywillems Nov 20, 2024
3153e27
o1vm/riscv32: implement mul_lo_signed
dannywillems Nov 20, 2024
f707007
o1vm/riscv32: implement mul_hi
dannywillems Nov 20, 2024
e0c1e89
o1vm/riscv32: implement M type instruction Mul
dannywillems Nov 20, 2024
83aec4b
o1vm/riscv32: implement mulh
dannywillems Nov 20, 2024
d8c8311
o1vm/riscv32: implement Mulhu
dannywillems Nov 20, 2024
188b7c6
o1vm/riscv32: remove unused mul_hi_lo_signed
dannywillems Nov 20, 2024
9a8de63
o1vm/riscv32: remove unused mul_hi_lo.
dannywillems Nov 20, 2024
250bce5
o1vm/riscv32: implement div_signed
dannywillems Nov 20, 2024
2340ce1
o1vm/riscv32: implement M type instruction div
dannywillems Nov 20, 2024
8f304aa
o1vm/riscv32: implement mod_signed
dannywillems Nov 20, 2024
75bb37a
Merge pull request #2771 from o1-labs/dw/implement-sll-riscv32
dannywillems Nov 20, 2024
de7f623
o1vm/riscv32: remove unused divmod_signed
dannywillems Nov 20, 2024
eaafc71
o1vm/riscv32: implement M type instruction Rem
dannywillems Nov 20, 2024
124d8be
Rename xi into polyscale
volhovm Nov 20, 2024
bad13ef
o1vm/riscv32: implement div for unsigned 32bits
dannywillems Nov 20, 2024
bf08bdf
o1vm/riscv32: implement mod_
dannywillems Nov 20, 2024
d7e039d
o1vm/riscv32: remove unused divmod
dannywillems Nov 20, 2024
b44fedc
o1vm/riscv32: implement M type instruction divu
dannywillems Nov 20, 2024
ade00c9
o1vm/riscv32: implement M type instruction Remu
dannywillems Nov 20, 2024
eb01801
o1vm/riscv32: implement mul_hi_signed_unsigned to be used for Mulhsu
dannywillems Nov 20, 2024
3a9e1bf
o1vm/riscv32: implement M type instruction Mulhsu
dannywillems Nov 20, 2024
761d053
Variable names in combine_polys: get rid of omegas
volhovm Nov 20, 2024
d83c807
Merge pull request #2772 from o1-labs/dw/implement-slt-riscv32
dannywillems Nov 20, 2024
9471b25
Merge pull request #2773 from o1-labs/dw/implement-sltu-riscv32
dannywillems Nov 20, 2024
b3b62cb
Merge pull request #2774 from o1-labs/dw/implement-xor-riscv32
dannywillems Nov 20, 2024
dc49843
Merge pull request #2775 from o1-labs/dw/implement-srl-riscv32
dannywillems Nov 20, 2024
a5975c4
Merge pull request #2776 from o1-labs/dw/implement-sra-riscv32
dannywillems Nov 20, 2024
e9b9cab
Merge pull request #2777 from o1-labs/dw/implement-or-riscv32
dannywillems Nov 20, 2024
430767c
Merge pull request #2778 from o1-labs/dw/implement-and-riscv32
dannywillems Nov 20, 2024
eeba19c
Merge pull request #2779 from o1-labs/dw/implement-itype-iterpret-doc
dannywillems Nov 20, 2024
46ab546
Merge pull request #2780 from o1-labs/dw/sketch-implement-stype
dannywillems Nov 21, 2024
4b85773
Merge pull request #2781 from o1-labs/dw/o1vm-riscv32-doc-and-credit
dannywillems Nov 21, 2024
d45fff8
Merge pull request #2782 from o1-labs/dw/sketch-sb-type-interpret
dannywillems Nov 21, 2024
5533511
Merge pull request #2783 from o1-labs/dw/sketch-u-type-interpret
dannywillems Nov 21, 2024
da16c87
Merge pull request #2784 from o1-labs/dw/sketch-uj-type-interpret
dannywillems Nov 21, 2024
3a955a9
Merge pull request #2785 from o1-labs/dw/itype-expand-missing-instruc…
dannywillems Nov 21, 2024
9708781
Merge pull request #2786 from o1-labs/dw/add-fibonacci-7-and-ignore-f…
dannywillems Nov 21, 2024
b8f787d
Merge pull request #2787 from o1-labs/dw/expand-m-type-instruction-in…
dannywillems Nov 21, 2024
e3ece75
Merge pull request #2788 from o1-labs/dw/pickles-mips-selectors-move-…
dannywillems Nov 21, 2024
82464fb
Merge pull request #2789 from o1-labs/dw/o1vm/riscv32-nb-of-instr
dannywillems Nov 21, 2024
aad3200
o1vm/mips: remove inverse_or_zero from interpreter trait
dannywillems Nov 21, 2024
e800dcf
Move combine_polys and related structs into utils.rs
volhovm Nov 20, 2024
42002f8
Rename erroneous d1_size into num_chunks in prover
volhovm Nov 20, 2024
0ba8482
More comments on ipa#open
volhovm Nov 20, 2024
d694a22
Improve combine_poly docs
volhovm Nov 20, 2024
b3ef6ea
Improve docs for PolynomialsToCombine
volhovm Nov 20, 2024
6542666
Improve docs for IPA, improve some variable names
volhovm Nov 20, 2024
051a8a7
Merge pull request #2759 from o1-labs/sai/elf-parse-test
dannywillems Nov 21, 2024
269edf0
Merge pull request #2814 from o1-labs/o1vm/mips/interpreter-remove-in…
dannywillems Nov 21, 2024
b48338f
Revert "add elf parser test"
dannywillems Nov 21, 2024
d9371ea
o1vm/riscv32: implement mul_hi_signed
dannywillems Nov 20, 2024
1e91814
o1vm/riscv32im: simplify mul_hi_signed
svv232 Nov 21, 2024
61a7514
Merge pull request #2816 from o1-labs/revert-riscv32i-test
dannywillems Nov 21, 2024
7f2d2fe
o1vm/mips: introduce scratch_state_inverse
dannywillems Nov 21, 2024
ff73fa2
o1vm/MIPS: intro a new column to keep track of values to be inverted
dannywillems Nov 21, 2024
52d5cd9
o1vm/mips/witness: introduce and call reset_scratch_state_inverse
dannywillems Nov 21, 2024
f108bf2
o1vm/mips/constraints: reset scratch state idx inverse
dannywillems Nov 21, 2024
8f37429
o1vm/mips: introduce scratch_inverse in the proof
dannywillems Nov 21, 2024
acc0253
o1vm/mips: use alloc_scratch_inverse for the inverse
dannywillems Nov 21, 2024
da3f830
o1vm/column: increase the total number of columns incl. inverses
dannywillems Nov 21, 2024
dcf661c
o1vm/column: add error message when assert is false
dannywillems Nov 21, 2024
ac0380b
o1vm/mips: simplify by removing unused variable
dannywillems Nov 21, 2024
a934839
o1vm/pickles: improve error message when panicking when picking col
dannywillems Nov 21, 2024
c65b14a
o1vm/pickles: incl scratch_size_inverse selection in get_all_columns
dannywillems Nov 21, 2024
3071eab
o1vm/pickles: regtest reg. arkworks batch inversion
dannywillems Nov 21, 2024
f4b52a7
o1vm/pickles: add scratch_state_inverse in the proof inputs
dannywillems Nov 21, 2024
be87dce
o1vm/mips: allocate correctly the inverse column
dannywillems Nov 21, 2024
a11a350
o1vm/mips: fix tests related to the new inverse scratch state
dannywillems Nov 21, 2024
bc8456e
Merge pull request #2790 from o1-labs/dw/riscv32-impl-mul-hi-signed
dannywillems Nov 21, 2024
bc42b02
o1vm/mips: rewrite offsets reg. column index in scratch state
dannywillems Nov 21, 2024
796267d
o1vm/mips: decreasing actual scratch state size by 40%
dannywillems Nov 21, 2024
ebcd6bb
o1vm/riscv32: implement mul_lo_signed
dannywillems Nov 20, 2024
95098af
o1vm/riscv32im: simplify mul_lo_signed implementation
dannywillems Nov 25, 2024
1ab1995
o1vm/riscv32im: improve documentation reg. semantic of op
dannywillems Nov 25, 2024
89b4085
o1vm/riscv32im: add semantic for MInstruction
dannywillems Nov 25, 2024
1f1ceb8
Merge pull request #2813 from o1-labs/o1vm/batch-inversion
dannywillems Nov 25, 2024
171e066
Merge pull request #2815 from o1-labs/o1vm/decrease-scratch-size
dannywillems Nov 25, 2024
6aaa8f6
o1vm/riscv32im: test decoding add
dannywillems Nov 25, 2024
520bd77
o1vm/riscv32im: test decoding sub
dannywillems Nov 25, 2024
c3808c9
o1vm/riscv32im: test decoding sll
dannywillems Nov 25, 2024
03a0f8a
o1vm/riscv32im: test decoding slt
dannywillems Nov 25, 2024
7fe1149
o1vm/riscv32im: test decoding sltu
dannywillems Nov 25, 2024
c12f578
o1vm/riscv32im: test decoding xor
dannywillems Nov 25, 2024
37d0db0
o1vm/riscv32im: test decoding srl
dannywillems Nov 25, 2024
f98062c
o1vm/riscv32im: test decoding sra
dannywillems Nov 25, 2024
b86aa1f
implementation for load half instruction for riscvi32
svv232 Nov 25, 2024
71c27a7
o1vm/riscv32im: test decoding or
dannywillems Nov 25, 2024
2245928
implementation for load byte in riscv32im
svv232 Nov 25, 2024
d4d42ae
o1vm/riscv32im: test decoding and
dannywillems Nov 25, 2024
b89ce1c
implementation for load byte unsigned riscv32im
svv232 Nov 25, 2024
83e423a
implementation for load half unsigned riscv32im
svv232 Nov 25, 2024
20b29d3
o1vm: reorganize dependencies in alphabetical order
dannywillems Nov 25, 2024
403763e
Merge pull request #2791 from o1-labs/dw/riscv32-impl-mul-lo-signed
dannywillems Nov 25, 2024
ba54734
o1vm/riscv32: implement mul_hi
dannywillems Nov 20, 2024
840066e
o1vm/riscv32: implement mul_lo
dannywillems Nov 20, 2024
4d833a2
o1vm/riscv32: implement M type instruction Mul
dannywillems Nov 20, 2024
8a2987c
Merge pull request #2827 from o1-labs/sai/load_half_riscv32im
dannywillems Dec 2, 2024
1b97e06
Merge pull request #2829 from o1-labs/sai/load_byte_riscv32im
dannywillems Dec 2, 2024
d2ecd19
Merge pull request #2831 from o1-labs/sai/load_byte_unsigned_riscv32im
dannywillems Dec 2, 2024
fdbc63c
Merge pull request #2792 from o1-labs/dw/riscv32-impl-mul-hi
dannywillems Dec 2, 2024
d507983
Merge pull request #2793 from o1-labs/dw/riscv32-impl-mul-lo
dannywillems Dec 2, 2024
f851298
Merge pull request #2794 from o1-labs/dw/riscv32/impl-mul
dannywillems Dec 2, 2024
93afc08
o1vm/riscv32: implement mulh
dannywillems Nov 20, 2024
e752cac
o1vm/riscv32: implement Mulhu
dannywillems Nov 20, 2024
4641725
o1vm/riscv32: remove unused mul_hi_lo_signed
dannywillems Nov 20, 2024
f07b581
o1vm/riscv32: remove unused mul_hi_lo.
dannywillems Nov 20, 2024
cc809da
Merge pull request #2833 from o1-labs/sai/load_half_unsigned_riscv32im
dannywillems Dec 2, 2024
c75ef56
Merge pull request #2795 from o1-labs/dw/riscv32/impl-mulh
dannywillems Dec 2, 2024
da64dcc
Merge pull request #2796 from o1-labs/dw/riscv32/impl-mulhu
dannywillems Dec 2, 2024
c7e2a58
Merge pull request #2797 from o1-labs/dw/o1vm/riscv-remove-mul-hi-lo-…
dannywillems Dec 2, 2024
93d7db1
Merge pull request #2798 from o1-labs/dw/o1vm/riscv-remove-mul-hi-lo
dannywillems Dec 2, 2024
3815c8a
o1vm/riscv32: implement div_signed
dannywillems Nov 20, 2024
bb6f118
o1vm/riscv32im: simplify div_signed
dannywillems Nov 25, 2024
7367e4b
o1vm/riscv32: implement M type instruction div
dannywillems Nov 20, 2024
4acdde0
Merge pull request #2799 from o1-labs/dw/o1vm/riscv32/implement-div-s…
dannywillems Dec 2, 2024
8d8c137
Merge pull request #2800 from o1-labs/dw/o1vm/riscv32/implement-m-typ…
dannywillems Dec 2, 2024
0ad5fea
o1vm/riscv32: implement mod_signed
dannywillems Nov 20, 2024
4e0220d
o1vm/riscv32im: simplify mod_signed
dannywillems Nov 25, 2024
77a50c4
o1vm/riscv32: remove unused divmod_signed
dannywillems Nov 20, 2024
deedbff
o1vm/riscv32: implement M type instruction Rem
dannywillems Nov 20, 2024
85639ca
o1vm/riscv32: implement div for unsigned 32bits
dannywillems Nov 20, 2024
c9207b8
o1vm/riscv32: implement mod_
dannywillems Nov 20, 2024
517924f
o1vm/riscv32im: rename mod_ in mod_unsigned for readability
dannywillems Nov 25, 2024
7482d1b
o1vm/riscv32: remove unused divmod
dannywillems Nov 20, 2024
06b07c2
Merge pull request #2801 from o1-labs/dw/o1vm/riscv32/implement-mod-s…
dannywillems Dec 2, 2024
4326735
Merge pull request #2802 from o1-labs/dw/o1vm/riscv32/remove-unused-d…
dannywillems Dec 2, 2024
574d76e
Merge pull request #2803 from o1-labs/dw/o1vm/riscv32/implement-m-typ…
dannywillems Dec 2, 2024
eb330fc
Merge pull request #2804 from o1-labs/dw/riscv32/implement-div
dannywillems Dec 2, 2024
3dd7fe6
Change comment notation to additive
volhovm Dec 3, 2024
2e4d754
Rename d1_size to n_chunks in IVC prover
volhovm Dec 3, 2024
57f62ae
Merge pull request #2811 from o1-labs/volhovm/rename-pickles-vars
volhovm Dec 3, 2024
b3dbfe0
Merge pull request #2805 from o1-labs/dw/riscv32/implement-mod_
dannywillems Dec 3, 2024
2060706
Merge pull request #2806 from o1-labs/dw/riscv32/remove-divmod
dannywillems Dec 3, 2024
e084008
o1vm/riscv32: implement M type instruction divu
dannywillems Nov 20, 2024
4c5bff9
o1vm/riscv32: implement M type instruction Remu
dannywillems Nov 20, 2024
1708293
o1vm/riscv32: implement mul_hi_signed_unsigned to be used for Mulhsu
dannywillems Nov 20, 2024
8da1a41
Merge pull request #2807 from o1-labs/dw/riscv32-impl-m-type-divu
dannywillems Dec 3, 2024
31a9b3f
Merge pull request #2808 from o1-labs/dw/riscv32-impl-m-type-remu
dannywillems Dec 3, 2024
71d6a09
Merge pull request #2809 from o1-labs/dw/riscv32-impl-mul-hi-signed-u…
dannywillems Dec 3, 2024
277cec8
o1vm/riscv32: implement M type instruction Mulhsu
dannywillems Nov 20, 2024
d0f9cb3
Merge pull request #2810 from o1-labs/dw/riscv32-impl-mulhsu
dannywillems Dec 4, 2024
54edc55
o1vm/riscv32im: improve documentation reg. semantic of op
dannywillems Nov 25, 2024
964cfeb
o1vm/riscv32im: add semantic for MInstruction
dannywillems Nov 25, 2024
3589aed
Merge pull request #2817 from o1-labs/dw/riscv32im-add-semantic-impl
dannywillems Dec 4, 2024
0917d01
Merge branch 'master' into o1vm/riscv32im/test-decoding-add
dannywillems Dec 4, 2024
673954a
CI/o1vm: deactivating path dependent execution
dannywillems Dec 4, 2024
e1875cf
Merge pull request #2819 from o1-labs/o1vm/riscv32im/test-decoding-add
dannywillems Dec 4, 2024
ea5cb0e
Merge branch 'master' into o1vm/riscv32im/test-decoding-sub
dannywillems Dec 4, 2024
a58943d
Merge pull request #2863 from o1-labs/ci/deactivate-conditional-actions
dannywillems Dec 4, 2024
9b2ad57
Mina-signer: make secret field of KeyPair public
dannywillems Nov 12, 2024
55c51b3
Merge pull request #2820 from o1-labs/o1vm/riscv32im/test-decoding-sub
dannywillems Dec 4, 2024
e0b822f
Merge branch 'master' into o1vm/riscv32im/test-decoding-sll
dannywillems Dec 4, 2024
abc1bbb
Merge pull request #2755 from o1-labs/dw/make-secret-field-public-min…
dannywillems Dec 4, 2024
388aaf0
Merge pull request #2821 from o1-labs/o1vm/riscv32im/test-decoding-sll
dannywillems Dec 4, 2024
0116f6c
Merge pull request #2822 from o1-labs/o1vm/riscv32im/test-decoding-slt
dannywillems Dec 4, 2024
f25d9d5
Merge pull request #2823 from o1-labs/o1vm/riscv32im/test-decoding-sltu
dannywillems Dec 4, 2024
55e9941
Merge pull request #2824 from o1-labs/o1vm/riscv32im/test-decoding-xor
dannywillems Dec 4, 2024
2c002d6
Merge pull request #2825 from o1-labs/o1vm/riscv32im/test-decoding-srl
dannywillems Dec 4, 2024
26fc376
Merge pull request #2826 from o1-labs/o1vm/riscv32im/test-decoding-sra
dannywillems Dec 4, 2024
25447f6
Merge pull request #2828 from o1-labs/o1vm/riscv32im/test-decoding-or
dannywillems Dec 4, 2024
578d17c
Merge pull request #2830 from o1-labs/o1vm/riscv32im/test-decoding-and
dannywillems Dec 4, 2024
0af1256
Merge pull request #2849 from o1-labs/o1vm/deps-reorg
dannywillems Dec 4, 2024
98e7c35
self helping Makefile
martyall Dec 5, 2024
cdbc90c
Merge pull request #2867 from o1-labs/martin/add-make-help
dannywillems Dec 5, 2024
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
5 changes: 0 additions & 5 deletions .cargo/config.toml

This file was deleted.

36 changes: 16 additions & 20 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,7 @@ jobs:
with:
rust_toolchain_version: ${{ matrix.rust_toolchain_version }}

- name: Rust Cache
- name: Apply the Rust smart cacheing
uses: Swatinem/rust-cache@v2

- name: Use shared OCaml setting up steps
Expand Down Expand Up @@ -134,7 +134,7 @@ jobs:
- name: Build cargo docs
run: |
eval $(opam env)
RUSTDOCFLAGS="-D warnings" cargo doc --all-features --no-deps
make generate-doc

#
# Coding guidelines
Expand Down Expand Up @@ -174,24 +174,20 @@ jobs:
eval $(opam env)
make nextest

- name: Run heavy tests without the code coverage
- name: Run non-heavy tests with the code coverage
if: ${{ matrix.rust_toolchain_version == env.RUST_TOOLCHAIN_COVERAGE_VERSION }}
run: |
eval $(opam env)
make nextest-heavy
# TODO: Re-enable this for tests with coverage data gathering.
# TODO: We intentionally disable the tests with the code coverage data gathering because
# TODO: Rust's code coverage instrumentation is not compatible with some of the optimizations that occur during release builds.
# make nextest-with-coverage
# make test-doc-with-coverage
# make generate-test-coverage-report

# - name: Use shared code coverage summary
# if: ${{ matrix.rust_toolchain_version == env.RUST_TOOLCHAIN_COVERAGE_VERSION }}
# uses: ./.github/actions/coverage-summary-shared

# - name: Use shared Codecov reporting steps
# if: ${{ matrix.rust_toolchain_version == env.RUST_TOOLCHAIN_COVERAGE_VERSION }}
# uses: ./.github/actions/codecov-shared
# with:
# token: ${{ secrets.CODECOV_TOKEN }}
make nextest-with-coverage
make test-doc-with-coverage
make generate-test-coverage-report

- name: Use shared code coverage summary
if: ${{ matrix.rust_toolchain_version == env.RUST_TOOLCHAIN_COVERAGE_VERSION }}
uses: ./.github/actions/coverage-summary-shared

- name: Use shared Codecov reporting steps
if: ${{ matrix.rust_toolchain_version == env.RUST_TOOLCHAIN_COVERAGE_VERSION }}
uses: ./.github/actions/codecov-shared
with:
token: ${{ secrets.CODECOV_TOKEN }}
13 changes: 8 additions & 5 deletions .github/workflows/gh-page.yml
Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,13 @@ name: Deploy Specifications & Docs to GitHub Pages

on:
push:
branches:
- master
branches: ["master"]

env:
OCAML_VERSION: "4.14.0"
RUST_TOOLCHAIN_VERSION: "nightly"
# This version has been chosen randomly. It seems that with 2023-11-16, it is
# broken. The compiler crashes. Feel free to pick any newer working version.
RUST_TOOLCHAIN_VERSION: "1.72"

jobs:
release:
Expand All @@ -30,10 +31,11 @@ jobs:
with:
ocaml_version: ${{ env.OCAML_VERSION }}

# This must be the same as in the section "Generate rustdoc locally" in the README.md
- name: Build Rust Documentation
run: |
eval $(opam env)
RUSTDOCFLAGS="--enable-index-page -Zunstable-options" cargo +nightly doc --all --no-deps
RUSTDOCFLAGS="--enable-index-page -Zunstable-options -D warnings" cargo doc --workspace --all-features --no-deps

- name: Build the mdbook
run: |
Expand All @@ -47,7 +49,8 @@ jobs:
mv ./target/doc ./book/book/html/rustdoc

- name: Deploy
uses: peaceiris/actions-gh-pages@v3
uses: peaceiris/actions-gh-pages@v4
if: github.ref == 'refs/heads/master'
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
publish_dir: ./book/book/html
92 changes: 92 additions & 0 deletions .github/workflows/o1vm-ci.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,92 @@
name: o1vm CI

on:
workflow_dispatch:
pull_request:
push:
branches:
- master

env:
# https://doc.rust-lang.org/cargo/reference/profiles.html#release
# Disable for the time being since it fails with the "attempt to multiply with overflow" error.
# Known issue yeat to be fixed.
# RUSTFLAGS: -Coverflow-checks=y -Cdebug-assertions=y
# https://doc.rust-lang.org/cargo/reference/profiles.html#incremental
CARGO_INCREMENTAL: 1
# https://nexte.st/book/pre-built-binaries.html#using-nextest-in-github-actions
CARGO_TERM_COLOR: always
# 30 MB of stack for Keccak tests
RUST_MIN_STACK: 31457280

jobs:
run_o1vm_with_cached_data:
name: Run o1vm with cached data
# We run only one of the matrix options on the toffee `hetzner-1` self-hosted GitHub runner.
# Only in this configuration we enable tests with the code coverage data gathering.
runs-on: ["ubuntu-latest"]
strategy:
matrix:
rust_toolchain_version: ["1.74"]
# FIXME: currently not available for 5.0.0.
# It might be related to boxroot dependency, and we would need to bump
# up the ocaml-rs dependency
ocaml_version: ["4.14"]
services:
o1vm-e2e-testing-cache:
image: o1labs/proof-systems:o1vm-e2e-testing-cache
volumes:
- /tmp:/tmp/cache
steps:
- name: Checkout repository
uses: actions/checkout@v4
with:
submodules: recursive

- name: Use shared Rust toolchain setting up steps
uses: ./.github/actions/toolchain-shared
with:
rust_toolchain_version: ${{ matrix.rust_toolchain_version }}

- name: Apply the Rust smart cacheing
uses: Swatinem/rust-cache@v2

- name: Use shared OCaml setting up steps
uses: ./.github/actions/ocaml-shared
with:
ocaml_version: ${{ matrix.ocaml_version }}

- name: Install the Python
uses: actions/setup-python@v5
with:
python-version: "3.13"
check-latest: true

- name: Install the Go
uses: actions/setup-go@v5
with:
go-version: "1.21.0"

- name: Install the Foundry
uses: foundry-rs/foundry-toolchain@v1

- name: Build the OP program
run: |
cd o1vm
make -C ./ethereum-optimism/op-program op-program
cd ..

- name: Start the local HTTP server
run: |
python -m http.server 8765 &

#
# Tests
#

- name: Execute o1vm in E2E flavor using cached data
run: |
eval $(opam env)
cd o1vm
unzip -q -o /tmp/o1vm-e2e-testing-cache.zip -d ./
RUN_WITH_CACHED_DATA="y" FILENAME="env-for-latest-l2-block.sh" O1VM_FLAVOR="pickles" STOP_AT="=3000000" ./run-code.sh
35 changes: 0 additions & 35 deletions .github/workflows/stale.yml

This file was deleted.

10 changes: 10 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,13 @@ build
tools/srs

.ignore
o1vm/env-for-*
o1vm/cpu.pprof
o1vm/snapshot-state*
o1vm/rpcs.sh
o1vm/meta.json
o1vm/out.json
o1vm/op-program-db*
o1vm/state.json
meta.json
state.json
6 changes: 3 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
[submodule "proof-systems-vendors"]
path = proof-systems-vendors
url = https://github.com/o1-labs/proof-systems-vendors.git
[submodule "o1vm/ethereum-optimism"]
path = o1vm/ethereum-optimism
url = https://github.com/ethereum-optimism/optimism.git
2 changes: 1 addition & 1 deletion .rustfmt.toml
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
indent_style = "Block"
imports_granularity = "Crate"
reorder_imports = true
reorder_imports = true
12 changes: 9 additions & 3 deletions CONTRIBUTING.md
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,8 @@ We have a list of easy task to start contributing. [Start over there](https://gi

## Setting up the project

Make sure you have the GNU `make` utility installed since we use it to streamline various tasks.
Windows users may need to use the `WSL` to run `make` commands.
Make sure you have the GNU `make` utility installed since we use it to streamline various tasks.
Windows users may need to use the `WSL` to run `make` commands.
For the complete list of `make` targets, please refer to the [Makefile](Makefile).

After the repository being cloned, run:
Expand Down Expand Up @@ -75,6 +75,12 @@ BIN_EXTRA_ARGS="-p poly-commitment" make nextest-all-with-coverage
```

Note: In example above we run tests for the `poly-commitment` package only.
You can also use the environment variable `BIN_EXTRA_ARGS` to select a specific
test to run. For instance:
```
BIN_EXTRA_ARGS="test_opening_proof" make nextest
```
will only run the tests containing `test_opening_proof`.

We build and run tests in `--release` mode, because otherwise tests execution can last for a long time.

Expand All @@ -96,7 +102,7 @@ Note: cargo can automatically fix some lints. To do so, add `--fix` to the `CARG
CARGO_EXTRA_ARGS="--fix" make lint
```

Formatting and lints are enforced by GitHub PR checks, so please be sure to have any errors produced by the above tools fixed before pushing the code to your pull request branch.
Formatting and lints are enforced by GitHub PR checks, so please be sure to have any errors produced by the above tools fixed before pushing the code to your pull request branch.
Please refer to [CI](.github/workflows/ci.yml) workflow to see all PR checks.

## Branching policy
Expand Down
Loading
Loading