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11 Open 4 Closed
11 Open 4 Closed
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Issues list

Segmentation Fault when make run-example-c-project-verilator
#28 opened Nov 7, 2024 by vanphuc1208
1
Regarding Simulation of 'make run-example-c-project-verilator' in GitLab for CVA-5
#25 opened Feb 3, 2024 by Tanishqgithub
1
Clarification Regarding Simulation of CVA-5 Processor
#24 opened Jan 31, 2024 by Tanishqgithub
1
State of AMO support
#21 opened Nov 2, 2023 by ramonwirsch
1
2
Interest in Flopoco-based FPU, Instruction invalidation on self-modifying code or Verilator Improvements?
#20 opened Nov 2, 2023 by ramonwirsch
4
Interrupts can lead to MEPC inconsistent with register state / actually retired operations or pointing to entirely illegal instructions
#19 opened Nov 2, 2023 by ramonwirsch
1
6
Hardware Setup
#18 opened Sep 21, 2023 by leloc0609
how to use jtag in AMD FGPA
#17 opened Aug 1, 2023 by mola1222
cva5 simulation using questasim
#14 opened May 16, 2023 by AhmedMostafa98
@e-matthews
6
Cache architecture of the previous version (Taiga) question Further information is requested
#11 opened Mar 6, 2023 by demyana123
@e-matthews
3
Cache architecture of the CVA5 processor? question Further information is requested
#10 opened Mar 2, 2023 by Mohamed1984
@e-matthews
3
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