Skip to content

@bluespec Bluespec, Inc.

Change the repository type filter

All

    Repositories list

    20 repositories

    • RISCV_gdbstub

      Public
      A gdbstub for connecting GDB to a RISC-V Debug Module
      C
      •
      Apache License 2.0
      •6•24•0•0•Updated Oct 7, 2024Oct 7, 2024

    • AWSteria_Infra

      Public
      "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
      VHDL
      •6•17•1•0•Updated Sep 26, 2024Sep 26, 2024

    • Toooba

      Public
      RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
      Verilog
      •
      Other
      •36•161•3•0•Updated Jul 25, 2024Jul 25, 2024

    • mcu-release

      Public
      A release repository for the mcu class of CPUs
      Bluespec
      •1•2•0•0•Updated Feb 28, 2024Feb 28, 2024

    • Tiny_TCM

      Public
      A resource constrained TCM implementation.
      Bluespec
      •0•0•0•0•Updated Feb 27, 2024Feb 27, 2024

    • mcu-core

      Public
      The source files comprising the MCU core
      Bluespec
      •0•0•0•0•Updated Feb 26, 2024Feb 26, 2024

    • riscv-openocd

      Public
      C
      •
      GNU General Public License v2.0
      •3•7•0•0•Updated Oct 30, 2023Oct 30, 2023

    • Flute

      Public
      RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
      Bluespec
      •
      Apache License 2.0
      •56•357•9•1•Updated Oct 19, 2023Oct 19, 2023

    • AWS_Generic_Getting_Started

      Public
      Python
      •0•0•1•0•Updated Aug 23, 2023Aug 23, 2023

    • brvf-tools

      Public
      A collection of tools used by various RISC-V projects
      Python
      •0•1•0•0•Updated Jul 28, 2023Jul 28, 2023

    • riscv-tools-feedstock

      Public
      Shell
      •
      BSD 3-Clause "New" or "Revised" License
      •7•0•0•0•Updated May 17, 2023May 17, 2023

    • RISCV_Debug_Module

      Public
      Bluespec
      •
      Apache License 2.0
      •4•6•0•0•Updated Jan 1, 2023Jan 1, 2023

    • CLINT

      Public
      Timer and SW interrupts module
      Bluespec
      •0•0•0•0•Updated May 30, 2022May 30, 2022

    • AHB-Lite

      Public
      AHB-Lite adapters, initiators and targets.
      Bluespec
      •2•2•0•0•Updated May 20, 2022May 20, 2022

    • PLIC

      Public
      Platform Level Interrupt Controller
      Bluespec
      •0•0•0•0•Updated May 11, 2022May 11, 2022

    • APB

      Public
      Bluespec
      •0•1•0•0•Updated May 5, 2022May 5, 2022

    • Near_Mem

      Public
      All the different flavours of near-mem modules may eventually reside here.
      Bluespec
      •0•1•0•0•Updated Feb 28, 2022Feb 28, 2022

    • Piccolo

      Public
      RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
      Verilog
      •
      Apache License 2.0
      •49•310•14•2•Updated Jan 23, 2022Jan 23, 2022

    • Accel_AES

      Public
      Verilog
      •
      Apache License 2.0
      •7•15•0•0•Updated Jun 1, 2019Jun 1, 2019

    • riscv-tools

      Public
      Shell
      •2•5•0•0•Updated Nov 9, 2018Nov 9, 2018