Skip to content

@merledu Micro Electronics Research Laboratory

Change the repository type filter

All

    Repositories list

    137 repositories

    • Athestia

      Public
      Clean slate application using NDN with Dilithium to enhance security in future internet technology
      0•2•0•0•Updated Oct 3, 2024Oct 3, 2024

    • SoC-Now-Generator

      Public
      An open source Mini SoC Generator which will generate SoC based on parameters.
      Verilog
      •1•1•8•0•Updated Oct 3, 2024Oct 3, 2024

    • jigsaw

      Public
      A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
      gpiochisel3sramspi-flashuart-protocolpllchisel-generatorspi-protocolperipheralssoc
      Scala
      •7•3•1•2•Updated Oct 3, 2024Oct 3, 2024

    • caravan

      Public
      A caravan equipped with API for creating bus protocols in Chisel with ease.
      chisel3ambachisel-generatoron-chip-networkwishbonecaravanbus-protocols
      Scala
      •
      Apache License 2.0
      •11•13•4•0•Updated Oct 3, 2024Oct 3, 2024

    • soc-studio

      Public
      0•0•0•0•Updated Oct 2, 2024Oct 2, 2024

    • KyberQuanta

      Public
      A Kyber768-90's Hardware Accelerator.
      Python
      •2•2•0•0•Updated Oct 1, 2024Oct 1, 2024

    • nucleusrv

      Public
      NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      fpgacpuriscv
      C
      •
      GNU General Public License v3.0
      •24•59•15•0•Updated Oct 1, 2024Oct 1, 2024

    • oxygen

      Public
      A RISC-V Simulator
      Python
      •
      GNU General Public License v3.0
      •2•1•0•0•Updated Oct 1, 2024Oct 1, 2024

    • vaquita

      Public
      Scala
      •
      GNU General Public License v3.0
      •6•12•0•1•Updated Sep 27, 2024Sep 27, 2024

    • rv-thunder

      Public
      RISC-V 32-bit CPU written in amaranth (python-lib)
      pythoniotfpgaverilogsystemcrisc-vamaranth
      Verilog
      •5•7•1•1•Updated Sep 23, 2024Sep 23, 2024

    • ArcheV

      Public
      RISC-V RV-32i RTL Benchmark for evaluating Large Language Models.
      Verilog
      •3•0•1•0•Updated Sep 20, 2024Sep 20, 2024

    • MERL-Attendance

      Public
      Python
      •1•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • baby-kyber-accelerator

      Public
      a dedicated hardware accelerator accelerating Baby Kyber Encryption operations on hardware level written in CHISEL HDL
      C++
      •0•0•0•0•Updated Sep 10, 2024Sep 10, 2024

    • CryptoCortex

      Public
      Python
      •1•0•0•0•Updated Aug 29, 2024Aug 29, 2024

    • BabyKyberAcceleratorCHISEL

      Public
      C++
      •0•0•0•0•Updated Aug 23, 2024Aug 23, 2024

    • Burq-Suite

      Public
      An All in one RISC-V Suite.
      JavaScript
      •4•5•0•0•Updated Aug 15, 2024Aug 15, 2024

    • nucleusrv-64

      Public
      NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      C
      •
      GNU General Public License v3.0
      •24•0•0•0•Updated Jul 23, 2024Jul 23, 2024

    • OpenTCAM

      Public
      An open-source Ternary Content Addressable Memory (TCAM) compiler.
      compilertcamsram-memoriespython
      Python
      •
      Apache License 2.0
      •10•19•0•1•Updated Jul 19, 2024Jul 19, 2024

    • zeusic-v

      Public
      RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks
      2•2•0•0•Updated Jul 4, 2024Jul 4, 2024

    • Merl-UIT-Simulator

      Public
      JavaScript
      •
      Other
      •6•1•0•3•Updated Mar 27, 2024Mar 27, 2024

    • xodus

      Public
      RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL
      Scala
      •
      GNU General Public License v3.0
      •1•1•0•0•Updated Mar 23, 2024Mar 23, 2024

    • magma-si

      Public
      Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
      acceleratormatrixchiselmatrix-multiplicationchisel3gemmchisel-generator
      Scala
      •
      GNU General Public License v3.0
      •3•9•4•2•Updated Mar 21, 2024Mar 21, 2024

    • Google-Summer-of-Code

      Public
      Project ideas list for Google Summer of Code.
      projectsriscvgsoc
      2•11•0•0•Updated Feb 1, 2024Feb 1, 2024

    • chisel

      Public
      Chisel: A Modern Hardware Design Language
      Scala
      •
      Apache License 2.0
      •591•0•0•0•Updated Feb 1, 2024Feb 1, 2024

    • caravel_Ghazi_SoC_II

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Jan 11, 2024Jan 11, 2024

    • Lib-Analyzer

      Public
      Lib Analyzer is an application which is used to analyze the cells in the liberty files.
      Python
      •1•2•2•0•Updated Dec 25, 2023Dec 25, 2023

    • cachefy

      Public
      CHISEL API for plug n play connection of Caches in CHISEL designs
      chiselchisel3chisel-generatorscala
      Scala
      •
      Apache License 2.0
      •1•3•0•0•Updated Dec 19, 2023Dec 19, 2023

    • magmasi_caravel

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 11, 2023Dec 11, 2023

    • tracer

      Public
      CHISEL based RVFI Tracer
      Scala
      •0•0•0•0•Updated Nov 30, 2023Nov 30, 2023

    • nucleus_rv

      Public
      NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      C
      •
      GNU General Public License v3.0
      •24•0•0•0•Updated Nov 7, 2023Nov 7, 2023