Merge branch 'release/v1.0.1'

builder/main.py

@@ -71,8 +71,7 @@ def generate_disassembly(target, source, env):
 def run_verilator(target, source, env):
     trace_file = os.path.join(env.subst("$BUILD_DIR"), "trace.vcd")
     if os.path.isfile(trace_file):
-        print("Trace file %s already exists" % trace_file)
-        return
+        os.remove(trace_file)
 
     cmd = [
         os.path.join(
@@ -85,7 +84,7 @@ def run_verilator(target, source, env):
 
     p = subprocess.Popen(cmd, cwd=env.subst("$BUILD_DIR"))
 
-    # Wait for sometime while data is being collected
+    # Wait for some time while data is being collected
     time.sleep(3)
     p.terminate()
 

examples/native-asm/platformio.ini

@@ -7,7 +7,7 @@
 ; Please visit documentation for the other options and examples
 ; http://docs.platformio.org/page/projectconf.html
 
-[env:swervolf_nexys]
+[env:rvfpga]
 platform = chipsalliance
 board = swervolf_nexys
 board_build.ldscript = ld/link.ld

examples/native-bare_c/platformio.ini

@@ -7,7 +7,7 @@
 ; Please visit documentation for the other options and examples
 ; http://docs.platformio.org/page/projectconf.html
 
-[env:swervolf_nexys]
+[env:rvfpga]
 platform = chipsalliance
 board = swervolf_nexys
 board_build.ldscript = ld/link.ld
@@ -17,7 +17,7 @@ board_build.ldscript = ld/link.ld
 ; debug_init_break = tbreak main
 
 ; Path to a bitstream used with "program_fpga" target
-board_build.bitstream_file = swervolf_0.7.bit
+; board_build.bitstream_file = swervolf_0.7.bit
 
 ; Path to Vivado project files for "generate_bitstream" target
 ; board_build.swervolf_run_tc = swervolf_0.6_run.tcl

examples/psp-hello-world/platformio.ini

@@ -7,7 +7,7 @@
 ; Please visit documentation for the other options and examples
 ; http://docs.platformio.org/page/projectconf.html
 
-[env:swervolf_nexys]
+[env:rvfpga]
 platform = chipsalliance
 board = swervolf_nexys
 framework = wd-riscv-sdk

examples/rtosal-freertos/platformio.ini

@@ -7,7 +7,7 @@
 ; Please visit documentation for the other options and examples
 ; http://docs.platformio.org/page/projectconf.html
 
-[env:swervolf nexys]
+[env:rvfpga]
 platform = chipsalliance
 board = swervolf_nexys
 framework = wd-riscv-sdk, freertos

platform.json

@@ -17,7 +17,7 @@
     "type": "git",
     "url": "https://github.com/platformio/platform-chipsalliance.git"
   },
-  "version": "1.0.0",
+  "version": "1.0.1",
   "frameworks": {
     "wd-riscv-sdk": {
       "package": "framework-wd-riscv-sdk",
@@ -45,7 +45,6 @@
       "version": "0.0.0-alpha+sha.ca4b2392d8"
     },
     "tool-openocd-riscv-chipsalliance": {
-      "optional": true,
       "type": "uploader",
       "owner": "platformio",
       "version": "~1.1000.0"