Merge branch 'release/v1.0.2'

platformio · Oct 12, 2020 · 9db56b9 · 9db56b9
2 parents 32a2f24 + 59b4eea
commit 9db56b9
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Showing 2 changed files with 7 additions and 7 deletions.
diff --git a/builder/main.py b/builder/main.py
@@ -76,7 +76,7 @@ def run_verilator(target, source, env):
     cmd = [
         os.path.join(
             platform.get_package_dir("tool-verilator-swervolf") or "",
-            "Vswervolf_core_tb",
+            env.BoardConfig().get("debug.verilator.binary", "Vswervolf_core_tb")
         ),
         "+ram_init_file=" + os.path.basename(source[0].get_path()),
         "+vcd=1",
@@ -176,7 +176,7 @@ def run_verilator(target, source, env):
 
 # Note: there is a precompiled bitstream in framework-wd-riscv-sdk package
 bitstream_file = os.path.abspath(
-    env.BoardConfig().get("build.bitstream_file", "swervolf_0.bit"))
+    board_config.get("build.bitstream_file", "swervolf_0.bit"))
 
 if "program_fpga" in COMMAND_LINE_TARGETS and not os.path.isfile(bitstream_file):
     sys.stderr.write("Error: Couldn't find bitstream file.\n")
@@ -199,7 +199,7 @@ def run_verilator(target, source, env):
                 % os.path.join(
                     platform.get_package_dir("framework-wd-riscv-sdk") or "",
                     "board",
-                    env.BoardConfig().get("build.variant", ""),
+                    board_config.get("build.variant", ""),
                 ),
                 "-s",
                 '"%s"'
@@ -241,7 +241,7 @@ def run_verilator(target, source, env):
                 '"%s"'
                 % os.path.join(
                     platform.get_package_dir("tool-verilator-swervolf") or "",
-                    "Vswervolf_core_tb",
+                    board_config.get("debug.verilator.binary", "Vswervolf_core_tb"),
                 ),
                 "+jtag_vpi_enable=1",
             ]
@@ -266,11 +266,11 @@ def run_verilator(target, source, env):
         env.Exit(1)
 
     vivado_tcl_script = os.path.abspath(
-        env.BoardConfig().get("build.swervolf_run_tc", "swervolf_0.6_run.tcl")
+        board_config.get("build.swervolf_run_tc", "swervolf_0.6_run.tcl")
     )
 
     vivado_design_project = os.path.abspath(
-        env.BoardConfig().get("build.swervolf_xpr", "swervolf_0.6.xpr")
+        board_config.get("build.swervolf_xpr", "swervolf_0.6.xpr")
     )
 
     for f in (vivado_tcl_script, vivado_design_project):

diff --git a/platform.json b/platform.json
@@ -17,7 +17,7 @@
     "type": "git",
     "url": "https://github.com/platformio/platform-chipsalliance.git"
   },
-  "version": "1.0.1",
+  "version": "1.0.2",
   "frameworks": {
     "wd-riscv-sdk": {
       "package": "framework-wd-riscv-sdk",