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APB interface #38

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Sep 5, 2024
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Merged

APB interface #38

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32 changes: 10 additions & 22 deletions hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -37,11 +37,10 @@ package chimera_pkg;
// SoC Config
localparam bit SnitchBootROM = 1;
localparam bit TopLevelCfgRegs = 1;
localparam bit FLLCfgRegs = 1;
localparam bit PadCfgRegs = 1;
localparam bit ExtCfgRegs = 1;

// SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, Fll cfg regs, Pad cfg regs
localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + FLLCfgRegs + PadCfgRegs;
// SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, External regs (PADs, FLLs etc...)
localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs;
localparam int ClusterDataWidth = 64;

localparam int SnitchBootROMIdx = 0;
Expand All @@ -52,15 +51,10 @@ package chimera_pkg;
localparam doub_bt TopLevelCfgRegsRegionStart = 64'h3000_1000;
localparam doub_bt TopLevelCfgRegsRegionEnd = 64'h3000_2000;

// PADs external configuration registers
localparam int PadCfgRegsIdx = 2;
localparam doub_bt PadCfgRegsRegionStart = 64'h3000_2000;
localparam doub_bt PadCfgRegsRegionEnd = 64'h3000_3000;

// FLL external configuration registers
localparam int FllCfgRegsIdx = 3;
localparam doub_bt FllCfgRegsRegionStart = 64'h3000_3000;
localparam doub_bt FllCfgRegsRegionEnd = 64'h3000_4000;
// External configuration registers: PADs, FLLs, PMU Controller
localparam int ExtCfgRegsIdx = 2;
localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000;
localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000;


localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;
Expand Down Expand Up @@ -110,14 +104,9 @@ package chimera_pkg;
cfg.RegExtNumRules = ExtRegNum;
cfg.RegExtRegionIdx = {8'h3, 8'h2, 8'h1, 8'h0}; // SnitchBootROM
cfg.RegExtRegionStart = {
FllCfgRegsRegionStart,
PadCfgRegsRegionStart,
TopLevelCfgRegsRegionStart,
SnitchBootROMRegionStart
};
cfg.RegExtRegionEnd = {
FllCfgRegsRegionEnd, PadCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd
ExtCfgRegsRegionStart, TopLevelCfgRegsRegionStart, SnitchBootROMRegionStart
};
cfg.RegExtRegionEnd = {ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd};

// ACCEL HART/IRQ CFG
cfg.NumExtIrqHarts = ExtCores;
Expand All @@ -133,8 +122,7 @@ package chimera_pkg;

// To move into cheshire TYPEDEF
localparam int unsigned RegDataWidth = 32;
localparam type addr_t = logic [DefaultCfg.AddrWidth-1:0];
// localparam type data_t = logic[DefaultCfg.AxiDataWidth];
localparam type addr_t = logic [ChimeraCfg[0].AddrWidth-1:0];
localparam type data_t = logic [RegDataWidth-1:0];
localparam type strb_t = logic [RegDataWidth/8-1:0];

Expand Down
24 changes: 4 additions & 20 deletions hw/chimera_top_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,8 +54,6 @@ module chimera_top_wrapper
output logic [ 31:0] gpio_o,
output logic [ 31:0] gpio_en_o,
// APB interface
output apb_req_t apb_fll_req_o,
input apb_resp_t apb_fll_rsp_i,
input apb_resp_t apb_rsp_i,
output apb_req_t apb_req_o

Expand Down Expand Up @@ -202,32 +200,18 @@ module chimera_top_wrapper
.usb_dp_oe_o ()
);

// FLL REG
reg_to_apb #(
.reg_req_t(reg_req_t),
.reg_rsp_t(reg_rsp_t),
.apb_req_t(apb_req_t),
.apb_rsp_t(apb_resp_t)
) i_fll_reg_to_apb (
.clk_i (soc_clk_i),
.rst_ni (rst_ni),
.reg_req_i(reg_slv_req[FllCfgRegsIdx]),
.reg_rsp_o(reg_slv_rsp[FllCfgRegsIdx]),
.apb_req_o(apb_fll_req_o),
.apb_rsp_i(apb_fll_rsp_i)
);

// PADs REG
// External REGs
reg_to_apb #(
.reg_req_t(reg_req_t),
.reg_rsp_t(reg_rsp_t),
.apb_req_t(apb_req_t),
.apb_rsp_t(apb_resp_t)
) i_pad_reg_to_apb (
) i_ext_reg_to_apb (
.clk_i (soc_clk_i),
.rst_ni (rst_ni),
.reg_req_i(reg_slv_req[PadCfgRegsIdx]),
.reg_rsp_o(reg_slv_rsp[PadCfgRegsIdx]),
.reg_req_i(reg_slv_req[ExtCfgRegsIdx]),
.reg_rsp_o(reg_slv_rsp[ExtCfgRegsIdx]),
.apb_req_o(apb_req_o),
.apb_rsp_i(apb_rsp_i)
);
Expand Down
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