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Scheremo
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viv-eth
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Hw: - Add memory island domain wrapper
- chimera_cfg_t struct & typedef for AXI signals
- New Memory island address mappin
Sw: Add support to build chehsire bootrom for mem island integration
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| input axi_narrow_req_t axi_narrow_req_i, | ||
| output axi_narrow_rsp_t axi_narrow_rsp_o, |
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At some point you may want to break up the chs xbar and add individual narrow ports to the memory island for each master, see https://github.com/pulp-platform/cheshire/blob/michaero/chimera/hw/cheshire_soc.sv#L247-L311
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Hw: - Add memory island domain wrapper
- chimera_cfg_t struct & typedef for AXI signals
- New Memory island address mappin
Sw: Add support to build chehsire bootrom for mem island integration
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Memory Island Integration
This PR relocates the Memory Island IP from Cheshire and integrates it into the Chimera SoC module. The goal is to isolate the memory into a separate domain, allowing it to be managed independently from the power domain perspective.
Added
HW:
SW: