Integrate Hyperbus peripheral

[sermazz]

This PR:

• integrates the Hyperbus peripheral in the Chimera top RTL

• integrates the HyperRAM VIP in the Chimera testbench

• adds an addressability test for the Hyperbus and adds it to the CI

• Config registers are still to be added add config registers to hyperbus #43

• What address range should we use for the HyperRAM? https://github.com/pulp-platform/chimera/blob/smazzola/hyperbus/hw/chimera_pkg.sv#L128-L130

[Lore0599]

Overall LGTM

[sermazz]

@Lore0599 @arpansur @Scheremo @adimauro-iis
CI is finally passing after the fixes on devel, we should now define the range we need for HyperRAM (https://github.com/pulp-platform/chimera/pull/47/files#diff-7310782802ac0d64363e8ceb9e90e54a5c0c858fc1e63688d48ad6964dd3fb4bR131). And also have a plan for #43.
If these are not blocking, we can merge.

[Scheremo]

@Lore0599 @arpansur @Scheremo @adimauro-iis CI is finally passing after the fixes on devel, we should now define the range we need for HyperRAM (https://github.com/pulp-platform/chimera/pull/47/files#diff-7310782802ac0d64363e8ceb9e90e54a5c0c858fc1e63688d48ad6964dd3fb4bR131). And also have a plan for #43. If these are not blocking, we can merge.

I think both are blocking but trivial to resolve. You can extend the register memory map range (0x3000_0000 - 0x4000_0000) contiguously with the config registers and map the hyperbus memory "somewhere reasonable" (why not 0x5000_0000?)

[Scheremo]

Looks mostly fine to me, some comments sprinkled throughout. Is there some consideration behind having two PHYs? I understand two endpoints (HyperRAM and HyperFlash), but that should only necessitate another CS pin.

[sermazz]

Should be ready to merge.

• I integrated Morit's fixes from b67f438 and further fixed some small stuff
• Fixed the linting
• Connected the hyperbus peripheral to the regbus by instantiating another external regbus port in Cheshire

You can check the last commits that I added. Let me know if there's any further feedback :)

[Scheremo]

Should be ready to merge.

• I integrated Morit's fixes from b67f438 and further fixed some small stuff
• Fixed the linting
• Connected the hyperbus peripheral to the regbus by instantiating another external regbus port in Cheshire

You can check the last commits that I added. Let me know if there's any further feedback :)

Hey Sergio, thanks for the effort! All my comments are satisfied; we might want to add a few more large-scale tests, but the RTL looks mergeable to me.

[Scheremo]

LGTM - please just fix the failing pipeline.