[TB]: Extend testbench to improve debugging

[Lore0599]

Extend Testbench for better observability

This PR introduces some few adjustment to the Testbench to improve the observability when printing a word with UART.
Additionally, it also modify some parameters due to some issues encountered when testing the Chimrea PD design.
the goal of this PR, is to end up with a shared version of the VIP module.

JTAG SBUSY Problem

The reason why the idle_cycles have been increased to 4000, is to work around an issue with the task jtag_poll_bit0. This task uses the Debug Module function read_dmi_exp_backoff, which should not be used for read operations with side effects, as reading SBData0 is one such operation.
For instance, if the clock signal is removed, something that can occur during FLL testing, the Debug Module may not complete the write operation before attempting to read SBData0. This results in the Debug Module appearing busy. Consequently, during the next iteration of the exponential backoff, the DMI resets without clearing the sbusy bit, which leaves the system in a perpetually unstable state.
This problem should be documented and addressed properly in a dedicated issue.

[sermazz]

There's a failing test for Fatal: vsim caught SIGTERM. Closing vsimk kernel., we can merge after fixing the CI.
Also make sure to open an issue with what we discussed about the hotfix at line https://github.com/pulp-platform/chimera/pull/53/files#diff-e7ab86558bbfd35750a5495e656e391742070643bd26b942056310b2c72ed69cR332