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ci #1285: Pull request #95 opened by SamuelRiedel
February 21, 2024 14:47 8m 12s sriedel/maintenance
February 21, 2024 14:47 8m 12s
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ci #1284: Commit ac22be6 pushed by SamuelRiedel
February 21, 2024 14:44 8m 3s sriedel/maintenance
February 21, 2024 14:44 8m 3s
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ci #1283: Commit 0c8ec8a pushed by SamuelRiedel
February 21, 2024 14:43 8m 35s sriedel/maintenance
February 21, 2024 14:43 8m 35s
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ci #1282: Commit 50e98f6 pushed by SamuelRiedel
February 21, 2024 14:42 8m 46s sriedel/maintenance
February 21, 2024 14:42 8m 46s
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ci #1281: Commit 7d805d0 pushed by SamuelRiedel
February 21, 2024 14:31 8m 11s sriedel/maintenance
February 21, 2024 14:31 8m 11s
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ci #1280: Commit 0f708a0 pushed by SamuelRiedel
February 21, 2024 14:27 7m 35s sriedel/maintenance
February 21, 2024 14:27 7m 35s
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ci #1279: Commit dc69d54 pushed by SamuelRiedel
February 21, 2024 14:10 8m 34s sriedel/maintenance
February 21, 2024 14:10 8m 34s
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ci #1278: Commit 60aabe1 pushed by SamuelRiedel
February 21, 2024 13:51 6m 46s sriedel/maintenance
February 21, 2024 13:51 6m 46s
ci
ci #1277: Scheduled
February 21, 2024 01:56 6m 48s main
February 21, 2024 01:56 6m 48s
Fix midend computation to support unaligned DMA requests
ci #1276: Pull request #94 opened by SamuelRiedel
February 20, 2024 17:28 11m 35s sriedel/idma
February 20, 2024 17:28 11m 35s
February 20, 2024 17:13 11m 42s
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ci #1274: Scheduled
February 20, 2024 01:55 6m 50s main
February 20, 2024 01:55 6m 50s
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ci #1273: Scheduled
February 19, 2024 01:57 7m 36s main
February 19, 2024 01:57 7m 36s
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ci #1272: Scheduled
February 18, 2024 01:59 7m 4s main
February 18, 2024 01:59 7m 4s
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ci #1271: Scheduled
February 17, 2024 01:55 7m 33s main
February 17, 2024 01:55 7m 33s
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ci #1270: Commit fb5a7e9 pushed by SamuelRiedel
February 16, 2024 17:55 7m 32s sriedel/maintenance
February 16, 2024 17:55 7m 32s
[DRAMsys 2.0] Terapool DRAMsys Merge Request
ci #1269: Pull request #93 opened by yichao-zh
February 16, 2024 15:48 10m 52s terapool_DRAM_RTL
February 16, 2024 15:48 10m 52s
[memcpy] Remove unused dump from kernel
ci #1266: Commit c35003a pushed by yichao-zh
February 16, 2024 11:51 7m 28s terapool_DRAM_RTL
February 16, 2024 11:51 7m 28s
[memcpy] Reduce transfer size for MinPool CI check
ci #1265: Commit 8d48533 pushed by yichao-zh
February 16, 2024 11:40 6m 38s terapool_DRAM_RTL
February 16, 2024 11:40 6m 38s
[memcpy] Reduce transfer size for MinPool CI check
ci #1264: Commit 6ddf359 pushed by yichao-zh
February 16, 2024 11:34 6m 54s terapool_DRAM_RTL
February 16, 2024 11:34 6m 54s
[Config] Complete MinPool config for CI checking
ci #1263: Commit fc5b8c7 pushed by yichao-zh
February 16, 2024 11:21 11m 23s terapool_DRAM_RTL
February 16, 2024 11:21 11m 23s
[Rebase] Rebase the DRAM work on top of main branch
ci #1262: Commit dd14942 pushed by yichao-zh
February 16, 2024 11:09 6m 6s terapool_DRAM_RTL
February 16, 2024 11:09 6m 6s
ci
ci #1261: Scheduled
February 16, 2024 01:56 6m 54s main
February 16, 2024 01:56 6m 54s
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