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Virtual Memory SV-32 Address Translation Scheme Tests and Covergroups #516

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Virtual Memory SV-32 Address Translation Scheme Tests and Covergroups #516

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63b31cb
SV32 Tests and Covergroups added
MuhammadHammad001 Oct 11, 2024
85219ae
macro file updated and header_file added
MuhammadHammad001 Oct 11, 2024
611ea9a
Merge branch 'dev' into sv32_tests_cov
UmerShahidengr Oct 14, 2024
b1f23c3
RVMODEL_HALT label added
MuhammadHammad001 Oct 18, 2024
54223bd
Merge branch 'dev' into sv32_tests_cov
UmerShahidengr Oct 18, 2024
473bf8d
Merge branch 'dev' into sv32_tests_cov
MuhammadHammad001 Oct 24, 2024
cd30e60
Update test.yml
MuhammadHammad001 Oct 24, 2024
7fcd037
Update test.yml
MuhammadHammad001 Oct 24, 2024
b27a8e0
alignment added for 4KB page boundry
MuhammadHammad001 Oct 24, 2024
2968a34
Merge branch 'sv32_tests_cov' of https://github.com/MuhammadHammad001…
MuhammadHammad001 Oct 24, 2024
bc0d2b9
model_test.h updated
MuhammadHammad001 Oct 25, 2024
d98ed33
removed hardware update tests and added its covergroups in a single file
MuhammadHammad001 Oct 25, 2024
b1671a4
model_test updated
MuhammadHammad001 Oct 25, 2024
69ab3e6
increase the size limit to 10GB
MuhammadHammad001 Oct 25, 2024
a48128b
Merge branch 'dev' into sv32_tests_cov
jamesbeyond Nov 4, 2024
7714b2f
Update Coverpoints to use translator -> optimized and more readable
MuhammadHammad001 Nov 12, 2024
1fe1818
Merge branch 'dev' into sv32_tests_cov
MuhammadHammad001 Nov 14, 2024
a079bb2
Move the Virtual Memory SV-32 Tests to follow directory structure
MuhammadHammad001 Nov 14, 2024
496c5f6
Move the PMP Covergroups to follow directory structure
MuhammadHammad001 Nov 21, 2024
77477c4
Move the PMP Covergroups to follow directory structure
MuhammadHammad001 Nov 21, 2024
d689026
Covergroup for MPRV test added
MuhammadHammad001 Nov 22, 2024
07dcfa6
MPRV test for S and U mode added
MuhammadHammad001 Nov 22, 2024
d2b365a
tvm, satp, rsw tests added
MuhammadHammad001 Dec 2, 2024
478a3b4
Updated the test to dump the correct value for walking ones
MuhammadHammad001 Dec 4, 2024
bb63582
tests and covergroups for the combination of mprv and sum bit added
MuhammadHammad001 Dec 4, 2024
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24 changes: 23 additions & 1 deletion coverage/sv32/rv32_vm_sv32.cgf
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Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,26 @@ misaligned_superpage:
'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0
'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0

# If MVPV bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault
MPRV_bit:
config:
- check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
mnemonics:
"{sw, csrrc, csrrs, csrrw, lw, jalr}": 0
op_comb:
'mode == "M" and (satp >> 31) == ${SATP_MODE_SV32}': 0
csr_comb:
'((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0
#check mstatus has: case1: MPP& U in MPP and case2: MPP& S in MPP
mstatus == {0x00020000, 0x00020800}: 0
val_comb:
'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None': 0
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@allenjbaum allenjbaum Dec 6, 2024 •
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You shouldn't be using numeric constants. use MSTATUS_MPRV and MSTATUS_MPP_S (you'll need to define that latter). You could define MSTATUS_MPP_U (==0) and MSTATUS_MPP_M (==MSTATUS_MPP) also to make it clearer

'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1': 0
#Fault Checks
'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0
'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1 and len_dptw == 2': 0


# If MXR bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault
MXR_bit:
config:
Expand Down Expand Up @@ -195,7 +215,7 @@ U_bit_sum_set_in_SMode:
'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0
'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0

#If SUM bit is set, then User mode pages can be accessed in the Supervisor mode.
#If SUM bit is NOT set, then User mode pages can NOT be accessed in the Supervisor mode, get a fault.
U_bit_no_sum_set_in_SMode:
config:
- check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
Expand Down Expand Up @@ -235,6 +255,7 @@ U_bit_set_in_UMode:
'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0
'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0

#If U bit is NOT set in U mode, then we will get load, store and fetch page faults.
U_bit_unset_in_UMode:
config:
- check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
Expand All @@ -252,6 +273,7 @@ U_bit_unset_in_UMode:
'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0
'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0

#If U bit is NOT set in S mode, then page should be accessed successfully.
U_bit_unset_in_SMode:
config:
- check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
Expand Down