Merge pull request #1 from vyoma-systems/operand_x0

updated operands in zilsd instruction

riscv_ctg/data/template.yaml

@@ -6,7 +6,8 @@ metadata:
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
-  pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  pair_regs_zcmlsd: &pair_regs_zcmlsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(0,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   c_pair_regs: &c_pair_regs "['x'+str(x) for x in range(8,16,2)]"
 
 aes32dsi:

riscv_ctg/data/zilsd.yaml

@@ -4,7 +4,7 @@ ldz:
     stride: 2
     sz: 'XLEN/8'
   rs1_op_data: *all_regs_mx0
-  rd_op_data: *pair_regs
+  rd_op_data: *pair_regs_zilsd
   rd_hi: 0
   isa: 
     - IZilsd
@@ -26,7 +26,7 @@ sdz:
     stride: 2
     sz: 'XLEN/8'
   rs1_op_data: *all_regs_mx0
-  rs2_op_data: *pair_regs
+  rs2_op_data: *pair_regs_zilsd
   rd_op_data: *all_regs
   rs2_hi: 0
   xlen: [32]
@@ -70,7 +70,7 @@ c.ldspz:
   sig:
     stride: 2
     sz: 'XLEN/8'
-  rd_op_data: *pair_regs_zilsd
+  rd_op_data: *pair_regs_zcmlsd
   rd_hi: 0
   xlen: [32]
   std_op:

sample_cgfs/dataset.cgf

@@ -171,6 +171,24 @@ datasets:
     x28: 0
     x30: 0
 
+  pair_regs_zilsd: &pair_regs_zilsd
+    x0: 0
+    x2: 0
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   c_regs: &c_regs
     x8: 0
     x9: 0

sample_cgfs/rv32zilsd.cgf

@@ -8,7 +8,7 @@ ld:
     rs1: 
       <<: *all_regs_mx0
     rd: 
-      <<: *pair_regs
+      <<: *pair_regs_zilsd
     op_comb: 
       <<: *ifmt_op_comb
     val_comb:
@@ -33,7 +33,7 @@ sd:
     rs1: 
       <<: *all_regs_mx0
     rs2: 
-      <<: *pair_regs
+      <<: *pair_regs_zilsd
     op_comb: 
         'rs1 != rs2': 0
     val_comb:
@@ -75,7 +75,7 @@ csdsp:
     opcode: 
       c.sdspz: 0
     rs2: 
-      <<: *pair_regs
+      <<: *pair_regs_zilsd
     val_comb:
         'imm_val > 0': 0
         'imm_val == 0': 0

sample_cgfs/rv32zilsd_priv.cgf

@@ -1,14 +1,14 @@
 misalign-sd:
   config:
     - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
-    - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*32.*I.*Zicsr.*)
   mnemonics:
     sdz: 0
   rs1: 
     <<: *all_regs_mx0
   rs2: 
-    <<: *pair_regs
+    <<: *pair_regs_zilsd
   val_comb:
     'ea_align == 1': 0
     'ea_align == 2': 0
@@ -21,14 +21,14 @@ misalign-sd:
 misalign-ld:
   config:
     - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
-    - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
-  cond: check ISA:=regex(.*32.*I.*)
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+  cond: check ISA:=regex(.*32.*I.*Zicsr.*)
   mnemonics:
     ldz: 0
   rs1: 
     <<: *all_regs_mx0
   rd: 
-    <<: *pair_regs
+    <<: *pair_regs_zilsd
   val_comb:
     'ea_align == 1': 0
     'ea_align == 2': 0