Merge pull request #1848 from riscv-software-src/fix-1846

Fix FCSR accesses under Zfinx
riscv-software-src · Oct 31, 2024 · fd0a927 · fd0a927
2 parents f0d4d42 + 1adf60f
commit fd0a927
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -1410,8 +1410,9 @@ float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t
 
 void float_csr_t::verify_permissions(insn_t insn, bool write) const {
   masked_csr_t::verify_permissions(insn, write);
-  require_fs;
-  if (!proc->extension_enabled('F') && !proc->extension_enabled(EXT_ZFINX))
+
+  if (!((proc->extension_enabled('F') && STATE.sstatus->enabled(SSTATUS_FS))
+        || proc->extension_enabled(EXT_ZFINX)))
     throw trap_illegal_instruction(insn.bits());
 
   if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) {
@@ -1431,7 +1432,8 @@ void float_csr_t::verify_permissions(insn_t insn, bool write) const {
 }
 
 bool float_csr_t::unlogged_write(const reg_t val) noexcept {
-  dirty_fp_state;
+  if (!proc->extension_enabled(EXT_ZFINX))
+    dirty_fp_state;
   return masked_csr_t::unlogged_write(val);
 }
 

diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
@@ -165,7 +165,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 #define require_extension(s) require(p->extension_enabled(s))
 #define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B));
 #define require_impl(s) require(p->supports_impl(s))
-#define require_fs          require(STATE.sstatus->enabled(SSTATUS_FS))
 #define require_fp          STATE.fflags->verify_permissions(insn, false)
 #define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS))
 #define require_vector_vs   require(p->any_vector_extensions() && STATE.sstatus->enabled(SSTATUS_VS))