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Zvk disassembler support (on top of PR 1303) #1388

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merged 1 commit into from
Jun 20, 2023

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Zvk: disassembler support

This is meant to be pulled after #1303 has gone in. Only one commit is relevant and all previous ones will disappear once rebased.

Add disassembler support for all instructions in Zvk extensions:

  • Zvbb (bitmanip)
  • Zvbc (carryless multiplication)
  • Zvkg (GMAC)
  • Zvkned (AES)
  • Zvknha / Zvknhb (SHA-256, SHA-512)
  • Zvksed (SM4)
  • Zvksh (SM3)

Macros are used to limit code duplication, following the example
of the base V extension. Because the V extension undefines some
of its macros after their use, there Zvk support does define some
similar macros.

Co-authored-by: Gianluca Guida gianluca@rivosinc.com
Signed-off-by: Eric Gouriou ego@rivosinc.com

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egouriou-rivos commented Jun 19, 2023

@aswaterman
@nibrunieAtSi5

I am not crazy about the macro duplications, neither between V and the Zvk extensions, nor between the Zvk extensions themselves. Because I followed the V example I undef the macros after each extension, leading to some duplication between extensions. Feedback is appreciated.

I wish we could use more functions, but I don't really see how to avoid macros when dealing with identifier generation (vror -> match_vror_vv, match_vror_vx, etc.).

riscv/encoding.h Outdated
Comment on lines 424 to 429
#define MATCH_AMOCAS_D 0x2800302f
#define MASK_AMOCAS_D 0xf800707f
#define MATCH_AMOCAS_Q 0x2800402f
#define MASK_AMOCAS_Q 0xf800707f
#define MATCH_AMOCAS_W 0x2800202f
#define MASK_AMOCAS_W 0xf800707f
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I assume those are side effects of the riscv-opcodes update (and not directly related to vector crypto) ?

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Indeed. The encoding update is the one from #1303. It is made from riscv-opcode's master branch at HEAD because the previous encoding update contained commits very close to (at?) HEAD but seemingly not from the master branch or any commit that appears in riscv-opcodes's repo.

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With the merge of #1303, those changes disappeared from this PR.

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I think the PR should have as base branch the branch of #1303, namely rivosinc:zvk-vector-crypto at least until the PR merge (this would make only the delta change appear for review in this PR).

Add disassembler support for all instructions in Zvk extensions:
 - Zvbb (bitmanip)
 - Zvbc (carryless multiplication)
 - Zvkg (GMAC)
 - Zvkned (AES)
 - Zvknha / Zvknhb (SHA-256, SHA-512)
 - Zvksed (SM4)
 - Zvksh (SM3)

Macros are used to limit code duplication, following the example
of the base V extension. Because the V extension undefines some
of its macros after their use, there Zvk support does define some
similar macros.

Co-authored-by: Gianluca Guida <gianluca@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Thanks. Auto-merge should do its thing once the PR clears CI.

@aswaterman aswaterman merged commit d2cfddd into riscv-software-src:master Jun 20, 2023
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Oddly, auto-merge took effect before CI passed. Please babysit the CI task and create a fixup PR if there are any failures.

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For the record the new version that got accepted had those changes:

  • rebase, making all commits disappear but the disassembler one;
  • fixed the vaes{ed}{mf}.{vv,vs} and vsm4r.{vv,vs} instructions to use the "_V" decoding, as they all are of the form " vd, vs2" instead of the "vs, vs2, vs1" that the _VV macros encode.

Thanks for the merge!

@egouriou-rivos egouriou-rivos deleted the zvk-disassembler branch June 20, 2023 08:02
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3 participants