Added the rest of 1:1 PseudoInstructions that don't need any changes …

…to be made

Co-authored-by: Alfredo Rodrigues <Alfredo.Rodrigues@synopsys.com>
Signed-off-by: Afonso Oliveira <Afonso.Oliveira@synopsys.com>

parse.py

@@ -119,7 +119,9 @@ def process_enc_line(line, ext):
             (msb, lsb) = arg_lut[a]
             for ind in range(lsb, msb + 1):
                 # overlapping bits
-                if encoding_args[31 - ind] != '-':
+                if encoding_args[31-ind] == encoding_args [31-ind]:
+                    continue
+                elif encoding_args[31 - ind] != '-':
                     logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}')
                     raise SystemExit(1)
                 encoding_args[31 - ind] = a

rv_d

@@ -24,3 +24,8 @@ fcvt.w.d  rd rs1 24..20=0 31..27=0x18 rm       26..25=1 6..2=0x14 1..0=3
 fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm       26..25=1 6..2=0x14 1..0=3
 fcvt.d.w  rd rs1 24..20=0 31..27=0x1A rm       26..25=1 6..2=0x14 1..0=3
 fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm       26..25=1 6..2=0x14 1..0=3
+
+#pseudoinstructions
+$pseudo_op rv_d::fsgnj.d  fmv.d  rd rs1  31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3
+$pseudo_op rv_d::fsgnjx.d fabs.d rd rs1  31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3
+$pseudo_op rv_d::fsgnjn.d fneg.d rd rs1  31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3

rv_f

@@ -29,6 +29,11 @@ fmv.w.x   rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
 $pseudo_op rv_f::fmv.x.w fmv.x.s   rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
 $pseudo_op rv_f::fmv.w.x fmv.s.x   rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
 
+#pseudointructions
+$pseudo_op rv_f::fsgnj.s  fmv.s   rd rs1 rs1 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3
+$pseudo_op rv_f::fsgnjx.s fabs.s  rd rs1 rs1 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3
+$pseudo_op rv_f::fsgnjn.s fneg.s  rd rs1 rs1 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3
+
 #CSRs
 $pseudo_op rv_zicsr::csrrs  frflags    rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrw  fsflags    rd rs1      31..20=0x001 14..12=1 6..2=0x1C 1..0=3

rv_i

@@ -70,3 +70,7 @@ $pseudo_op rv_i::sltu   snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0=
 $pseudo_op rv_i::slt    sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3
 $pseudo_op rv_i::slt    sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3
 
+$pseudo_op rv_i::jalr   jalr rs1    31..20=0 14..12=0 11..7=0x01 6..2=0x19 1..0=3
+$pseudo_op rv_i::jalr   jr   rs1    31..20=0 14..12=0 11..7=0x0  6..2=0x19 1..0=3
+$pseudo_op rv_i::jal    jal  jimm20                   11..7=0x01 6..2=0x1b 1..0=3
+$pseudo_op rv_i::jal    j    jimm20                   11..7=0x0  6..2=0x1b 1..0=3

rv_zicsr

@@ -1,6 +1,16 @@
-csrrw     rd rs1 csr 14..12=1 6..2=0x1C 1..0=3
+csrrw     rd rs1 csr        14..12=1 6..2=0x1C 1..0=3
 csrrs     rd rs1 csr        14..12=2 6..2=0x1C 1..0=3
 csrrc     rd rs1 csr        14..12=3 6..2=0x1C 1..0=3
 csrrwi    rd csr zimm       14..12=5 6..2=0x1C 1..0=3
 csrrsi    rd csr zimm       14..12=6 6..2=0x1C 1..0=3
 csrrci    rd csr zimm       14..12=7 6..2=0x1C 1..0=3
+
+#pseudoinstructions
+$pseudo_op rv_zicsr::csrrs csrr     rd csr      19..15=0x0 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrw csrw     rs1 csr     14..12=1 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs csrs     rs1 csr     14..12=2 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrc csrc     rs1 csr     14..12=3 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrwi csrwi   csr zimm    14..12=5 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrsi csrsi   csr zimm    14..12=6 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrci csrci   csr zimm    14..12=7 11..7=0x0 6..2=0x1C 1..0=3
+