…iscv#191)

* V extension general framework and configuration setting instructions

* Update model/riscv_insts_vext_utils.sail

fix a typo

Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Signed-off-by: BrighterW <xinlai.w@rioslab.org>

* Update model/riscv_insts_vext_vset.sail

* Revisions after Nov 22 meeting

* Update effect matching for functions in riscv_vlen.sail

* Fix code formatting issues

* Update model/riscv_insts_vext_utils.sail

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>

* Fix coding style issues

* Update vset instructions

Signed-off-by: BrighterW <xinlai.w@rioslab.org>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>
Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

* Add vector load / store instructions

* Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code

* Update vstart setting in vector load / store instructions

* Remove unnecessary assert statements in vector instructions

* Fix bugs in vleff instructions and revise coding styles

* Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure

* Add vector arithmetic & mask instructions

* Update vector EEW and EMUL checking function

* Add vector instruction illegal check functions

* Adjust code formatting for vector instruction illegal check functions

Merge approved by team at tech-golden-model meeting on 2023-03-14.

* Add vector floating-point instructions

* Update vector floating-point conversion instructions

* Update copyright headers for vector extension code

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Co-authored-by: xwan <xinlai.wan@rivai.ai>

* Add vector mask and reduction instructions

* Fix register overlap check in vector mask instructions

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Co-authored-by: xwan <xinlai.wan@rivai.ai>

To support the implementation of Zvkb extensions in SAIL, this
creates the necessary infrastructure(i.e., a file to hold it, and the
extension macro), preparing the tree for the Zvkb implementation.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Vector rotate left by vector(.vv) or scalar(.vx).

The elements in vs2 are rotated left by the rotate amount
specified by either the cotrresponding elements of vs1 (vector-vector),
or integer register rs1 (vector-scalar). Only the low log2(SEW) bits
of the rotate-amount value are used, all other bits are ignored

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Vector rotate right by vector/scalar/immediate.

The elements in vs2 are rotated right by the rotate amount
specified by either the corresponding elements of vs1 (vector-vector),
integer register rs1 (vector-scalar), or an immediate value
(vector-immediate). Only the low log2(SEW) bits of the rotate-amount
value are used, all other bits are ignored.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Vector Reverse Bits in Bytes, a bit reversal is
performed on the bits of each byte.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Vector Reverse Bytes

A byte reversal is performed on each element of vs2, effectively
performing an endian swap.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Bitwise And-Not.

Each bit of Op1 is inverted and logically ANDed with the
corresponding bits in vs2. In the vector- scalar version,
"Op1" is the sign-extended or truncated value in scalar register
rs1. In the vector-vector version, Op1 is vs1.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Produces the low half of 128-bit carry-less product.

Each 64-bit element in the vs2 vector register is carry-less
multiplied by either each 64-bit element in vs1 (vector-vector), or
the 64-bit value from integer register rs1 (vector-scalar). The
result is the least significant 64 bits of the carry-less product.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>

Vector Carry-less Multiply by vector or scalar - returning
high half of product.

Each 64-bit element in the vs2 vector register is carry-less
multiplied by either each 64-bit element in vs1 (vector-vector), or
the 64-bit value from integer register rs1 (vector-scalar). The
result is the most significant 64 bits of the carry-less product.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>