Setting F=0 and D=1 should result in both F and D being cleared

[ahadali-10x]

Changed

• Updated legalize_misa function in the riscv_sys_regs.sail in the model/ directory to add condition by setting F=0 and D=1 should clear both F and D.

Issue Fixed

• Fix for issue Setting F=0 and D=1 should result in both F and D being cleared #300

[github-actions]

Unit Test Results

712 tests  ±0   712 ✔️ ±0   0s ⏱️ ±0s
    6 suites ±0       0 💤 ±0 
    1 files   ±0       0 ❌ ±0 

Results for commit e9ee198. ± Comparison against base commit 24e3e68.

♻️ This comment has been updated with latest results.

[Timmmm]

This looks correct to me.

[ahadali-10x]

@billmcspadden-riscv @scottj97 Kindly review the changes.

[billmcspadden-riscv]

@ahadali-10x : please add the following reference to your commit message:

"Per section 3.1.1 of the Privileged Spec ("Machine ISA Register misa"), ...."

[billmcspadden-riscv]

This looks correct to me.

[ahadali-10x]

@billmcspadden-riscv This PR can be merged now.

[jrtc27]

Commit message was poorly formatted, subject was too long and contained all the detail, rather than a short subject with a detailed body.

[Alasdair]

Commit message looks fine to me. Says precisely what was fixed. Do we have precise rules on what a commit message should be in the style guide?

[jrtc27]

No, because it’s standard practice for any well-managed open source project. You can tell it’s not a good commit message because GitHub cuts the subject off; were it correctly written the subject would be short enough to not be cut off. Git’s own manpage for the commit command documents this best practice (though 50 characters is a bit aggressive, IIRC GitHub caps at 80:) https://manpages.debian.org/bookworm/git-man/git-commit.1.en.html#DISCUSSION

[Timmmm]

Ah yeah I think Jessica is right - we might be looking at different things. The PR title is fine:

Setting F=0 and D=1 should result in both F and D being cleared

(except that it's a description of the bug, not the fix)

The commit message is very long and not in the normal commit message style:

Per section 3.1.1 of the Privileged Spec (Machine ISA Register misa): F/D both should be disabled if F=0

Probably should have been something like

Clear misa F and D bits when F=0 and D=1

With the spec reference in the body.

Relatively minor issue IMO though.