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Setting F=0 and D=1 should result in both F and D being cleared #301

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Sep 26, 2023
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Setting F=0 and D=1 should result in both F and D being cleared #301

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6 changes: 3 additions & 3 deletions model/riscv_sys_regs.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -164,10 +164,10 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
else {
/* Suppress enabling C if C was disabled at boot (i.e. not supported) */
let m = if not(sys_enable_rvc()) then m else update_C(m, v.C());
/* Handle updates for F/D. */
if not(sys_enable_fdext()) | (v.D() == 0b1 & v.F() == 0b0)
/* Suppress updates to misa.{f,d} if disabled at boot */
if not(sys_enable_fdext())
then m
else update_D(update_F(m, v.F()), v.D())
else update_D(update_F(m, v.F()), v.D() & v.F())
}
}

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