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Add read-only CSR MCONFIGPTR #422

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merged 1 commit into from
Apr 24, 2024

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Alasdair
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@Alasdair Alasdair commented Mar 1, 2024

This PR is a rebased version of: #293

Original description:

CSR MCONFIGPTR is defined in RISCV priv spec 1.12 but is missing from the RISC-V SAIL model. This commit adds the read-only CSR MCONFIGPTR.

CSR MCONFIGPTR is defined in RISCV priv spec 1.12 but is missing from the
RISC-V SAIL model. This commit adds the read-only CSR MCONFIGPTR.

Co-authored-by: Dan Smathers <dan.smathers@seagate.com>
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github-actions bot commented Mar 1, 2024

Test Results

712 tests  ±0   712 ✅ ±0   0s ⏱️ ±0s
  6 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 3433011. ± Comparison against base commit c287c34.

@dansmathers
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dansmathers commented Mar 3, 2024

FWIW I ran this pull against riscv-non-isa/riscv-arch-test#381 and sail-riscv signature now matches riscv-isa-sim
snippets from sail-riscv log:
read of mconfigptr returns 0
[98] [M]: 0x80000200 (0xF1502373) csrrs t1, mconfigptr, zero
CSR mconfigptr -> 0x00000000
x6 <- 0x00000000

write to mconfigptr causes illegal-instruction exception
[101] [M]: 0x8000020C (0xF1539073) csrrw zero, mconfigptr, t2
trapping from M to M to handle illegal-instruction

@Timmmm
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Timmmm commented Apr 24, 2024

@billmcspadden-riscv this is ready to merge.

@billmcspadden-riscv billmcspadden-riscv merged commit a39a1ac into riscv:master Apr 24, 2024
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5 participants