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Add read-only CSR MCONFIGPTR #293
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The diff itself looks fine |
Hi, anything else I need to do to get this merged into sail? FYI @billmcspadden-riscv |
You haven't done anything to the commit. The PR subject and body is not the same as the commit subject and body. |
And you still reference the TG in the PR's message, which isn't meaningful. It being used for unified discover is, and it being in Priv 1.12 for that purpose is, but the TG is meaningless. It's just a group of people that form an organisational structure. It's like saying "CSR fflags is being used for floating point by the unprivileged architecture standing committee". |
Ok. Updated. ok to merge? |
Hi Dan.
We'll discuss it in tomorrow's golden model meeting.
Bill Mc.
…On Mon, Aug 21, 2023 at 5:25 PM Dan Smathers ***@***.***> wrote:
Ok. Updated. ok to merge?
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No it's not. The commit is still unchanged. Please fix the commit message like I said. |
I don't see an easy way to do that using the github gui. Feel free to edit. |
Correct, there is not. You should be using a Git client, because the GitHub web interface is extremely limited. This admission is also rather concerning since, if you were using the web interface to create this PR, that means you cannot possibly have tested it locally, right? |
It was tested against sail and spike using riscof. |
Then use your Git client with the repository you cloned for RISCOF? I don't understand why the web GUI is a problem in that case. |
Also surely you mean just Spike there, given you're editing the Sail model... |
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This looks ok to me.
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Blocking on getting an appropriate commit message
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The instantiation of the CSR looks correct to me. However, two issues need to be addressed.
- How will this register be initialized? I suggest a command line argument be added to
supply the value to the register. This code can be found in c_emulator/riscv_sim.c I can help with the implementation of the command line switch. - The priv spec has verbiage concerning the legal value contained in the CSR. Here's the pertinent text:
The pointer alignment in bits must be no smaller than the greatest supported MXLEN: i.e., if the
greatest supported MXLEN is 8 × n, then mconfigptr[log2 n-1:0] must be zero.
This must be checked. I think it would be acceptable to check the value as you are processing the command line argument.
I think this should be merged as is (after the commit message is changed).
There are plenty of similar registers that do not have a way of setting them yet ( I think the alignment checking can be done at a later date too. (The spec does not say what should happen if the pointer is not appropriately aligned anyway, so it's unclear what the model should do - if anything.) |
@dansmathers did you mean to close this? |
yes. I had created it with a fork instead of a branch so my understanding it was preventing me creating other branches. not sure it was worth dealing with commit message corrections. it's easy enough for someone else to implement. |
If it helps, for future reference, before making a PR, you can do Updating a commit message is either |
If you like I can re-create your commit with an updated commit message |
It's just simple additions to the following files: riscv_csr_map.sail:mapping clause csr_name_map = 0xF15 <-> "mconfigptr" thanks for offering to assist. |
Ok, I've opened a new pull request here #422 the contents should be the same I think |
CSR MCONFIGPTR is defined in RISCV priv spec 1.12 but is missing from the RISC-V SAIL model. This PR adds the read-only CSR MCONFIGPTR.