Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Minor style fixes #476

Merged
merged 1 commit into from
May 23, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 0 additions & 1 deletion model/riscv_fetch.sail
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,6 @@

function isRVC(h : half) -> bool = not(h[1 .. 0] == 0b11)

val fetch : unit -> FetchResult
function fetch() -> FetchResult =
/* fetch PC check for extensions: extensions return a transformed PC to fetch,
* but any exceptions use the untransformed PC.
Expand Down
7 changes: 3 additions & 4 deletions model/riscv_step.sail
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,7 @@ function step(step_no : int) -> bool = {
},
None() => {
/* the extension hook interposes on the fetch result */
let f : FetchResult = ext_fetch_hook(fetch());
match f {
match ext_fetch_hook(fetch()) {
/* extension error */
F_Ext_Error(e) => {
ext_handle_fetch_check_error(e);
Expand All @@ -57,10 +56,10 @@ function step(step_no : int) -> bool = {
if haveRVC() then {
nextPC = PC + 2;
(execute(ast), true)
} else {
} else {
handle_illegal();
(RETIRE_FAIL, true)
}
}
},
F_Base(w) => {
instbits = zero_extend(w);
Expand Down
Loading