replace vxrm with vcsr[vxrm]

[rez5427]

When I run the vasub test file from the riscv-vector-test suite, I encountered a discrepancy between the outputs of Sail-RISCV and Spike, as shown in the image (highlighted in red). The issue stems from the function get_fixed_rounding_incr, which is incorrectly using the vxrm[1..0] bits instead of vcsr[vxrm]. The vxrm register is not being set by a CSR instruction; it is initialized to zero and remains zero throughout the execution, causing this mismatch.

[Timmmm]

Presumably this issue also exists for vxsat? I think we should also fix the duplicate read_csr and write_csr clauses at the same time.

[github-actions]

Test Results

396 tests  ±0   396 ✅ ±0   0s ⏱️ ±0s
  4 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit dae4fc0. ± Comparison against base commit b63b12f.

♻️ This comment has been updated with latest results.

[rez5427]

Is it appropriate to remove the registers vxrm and vxset in this context?

[Alasdair]

I don't think vxrm and vxsat should be actual Sail registers no, I think they are just parts of vcsr that should be accessible via the read_csr and write_csr functions.

[Alasdair]

Note: we should make sure to squash these commits before merging.