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1. SW-HW-co-simulation-of-an-IOT-architecture-built-on-ARM-processor SW-HW-co-simulation-of-an-IOT-architecture-built-on-ARM-processor Public

   This repo contains the Source code of a Software-Hardware co-simulation performed to mimic an "IoT architecture, built on top of ARM processor". A simple bus with inspiration from the Transaction L…

   C++ 1

2. TAPController_VHDL TAPController_VHDL Public

   -> IEEE Standard 1149.1 -> 16-state Finite State Machine . The Test Access Protocol is a separate Test and Debug block implemented for state checks of all the Registers. While entering the Test Mod…

   VHDL

3. RISC-V-RegisterSet-32-bit-_ScanTestable_VHDL RISC-V-RegisterSet-32-bit-_ScanTestable_VHDL Public

   A set of 32 Registers (32-bit wide) according to RISC-V architecture --> 1 write, 2 reads. Implemented in VHDL. This RegisterSet can be ScanTestable using a TAP controller.

   VHDL

4. RISC-V-single-cycle-processor-according-Hennessy-Patterson RISC-V-single-cycle-processor-according-Hennessy-Patterson Public

   The design implements a single-cycle RISC-V processor, according to the Hennessy-Patterson architecture. RTL designed using SystemVerilog and achieved Synthesis Flow using Xilinx Vivado 2023.2.

   SystemVerilog